Improvement of threshold voltage deviation in damascene metal gate transistors

MLA

Yagishita, Atsushi, et al. “Improvement of Threshold Voltage Deviation in Damascene Metal Gate Transistors.” IEEE Transactions on Electron Devices, vol. 48, no. 8, Aug. 2001, p. 1604. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsggo&AN=edsgcl.77454007&authtype=sso&custid=ns315887.

APA

Yagishita, A., Saito, T., Nakajima, K., Inumiya, S., Matsuo, K., Shibata, T., Tsunashima, Y., Suguro, K., & Arikado, T. (2001). Improvement of threshold voltage deviation in damascene metal gate transistors. IEEE Transactions on Electron Devices, 48(8), 1604.

Chicago

Yagishita, Atsushi, Tomohiro Saito, Kazuaki Nakajima, Seiji Inumiya, Kouji Matsuo, Takeshi Shibata, Yoshitaka Tsunashima, Kyoichi Suguro, and Tsunetoshi Arikado. 2001. “Improvement of Threshold Voltage Deviation in Damascene Metal Gate Transistors.” IEEE Transactions on Electron Devices 48 (8): 1604. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsggo&AN=edsgcl.77454007&authtype=sso&custid=ns315887.