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Test raises questions about VHDL/Verilog interoperability

Authors :
Meyer, Ernest
Source :
Computer Design. February 1, 1990, Vol. 29 Issue 3, p30, 3 p.
Publication Year :
1990

Abstract

Test raises questions about VHDL/Verilog interoperability If the VHSIC hardware description language (VHDL) is going to be used for documenting designs, then a particular VHDL file must produce an unambiguous […]

Details

Language :
English
ISSN :
00104566
Volume :
29
Issue :
3
Database :
Gale General OneFile
Journal :
Computer Design
Publication Type :
Academic Journal
Accession number :
edsgcl.8154800