Obtaining silicide free spacers by optimizing sputter etch for deep submicron CMOS processes

In this paper, we have shown that the sputter etch before cobalt deposition during the silicide processing of a deep submicron CMOS device fabrication needs to be optimized in order to eliminate a detrimental origin of gate (G) to source (S)/drain (D) bridging. It is known that Co cannot reduce even a thin layer of native oxide. Therefore, it is necessary to ensure that Co is deposited on a very clean Si surface. To ensure this, an in-situ sputter etch is commonly conducted before Co deposition. It is observed that this sputter etch process can sputter Si from the S/D area and deposit them on the sidewall spacer (SWS). This sputtered Si in turn will react with deposited Co and form silicide. The worst case leakage currents from poly-Si to composite for long (10 m) and narrow (0.18 micron) poly lines are shown to be on the order of milliampere. Transmission electron microscope (TEM) micrographs included show the existence of cobalt silicide layers (~ 8 nm thick) over sidewall spacer. The silicide thickness on the sidewall spacer is correlated with resistance value calculated from current and voltage (I-V) measurements. The need for optimizing the sputter etch recipe has been validated by TEM and I-V measurements. Index Terms--CMOS processing, cobalt silicide, G to S/D bridging, sidewall spacer, sputter etch.