Embedded DRAM design and architecture for the IBM 0.11-[micro]m ASIC offering

This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM third-generation embedded dynamic random-access memory (DRAM) for the IBM Blue Logic[R] 0.11-[micro]m application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM.