電流模式積體電路測試與所衍伸Wilson電流鏡應用電路

[[abstract]]IEEE 1149.1 Boundary Scan測試標準已被廣泛的應用在數位電路的領域。但隨著SoC的發展，許多晶片中都同時包含數位電路和類比電路，所以在這一篇論文之中我們提出Current Mode Boundary Scan Cell 對類比電流模式電路做測試，來增加對類比電流模式電路內部節點的可控制性和可觀察性，減少測試電路的時間。而且數位部分之控制與解碼電路皆與IEEE 1149.1 (JTAG)測試標準相同，因此極容易與數位電路整合，以作為混合訊號超大型積體電路測試之使用。本論文採用的是TSMC 0.35μm 2p4m製程，供應電壓為3.3V來設計完成。 論文中我們還延伸威爾森電流鏡電路(WCM)成為差動感應放大器，其對電流能夠進行高速高靈敏的比較並且僅消耗微瓦的功率(0.164mW)，進而衍伸應用到運算放大器(頻寬3.6MHz, 負載為100pF, 功率消率0.54mW, THD為-46dB)、測試Flash Memory電晶體的最高和最低的門檻電壓(Vth)單元、與MOS 電流模式邏輯電路。應用在測試Flash Memory電晶體上，可使Testing Efficiency更好。應用在MOS Current Mode Logic上，採用TSMC 0.18μm 1p6m製程，供應電壓為1.8V時，我們以所提出的Dynamic WCM-based Current Mode Logic(DyWCML)電路，設計一個四位元加法器，工作頻率可達到1.5GHz，功率消耗僅為4.6mW，是目前文獻中最佳的。
[[abstract]]The IEEE Boundary Scan Standard 1149.1 has been widely used for digital circuit testing. But with the development of SoC, many chips include digital and analog circuits simultaneously. Therefore, in this thesis we propose current mode boundary scan mechanism to test analog current mode circuits. It is efficient for analog testing since it increase the controllability and observability of internal nodes in analog current mode circuits. Furthermore, the digital control and the decoding circuits are compatible with the IEEE 1149.1(JTAG) test standard. Thus by using the proposed mechanism it is easy to integrate analog cores with the digital ones and thus the mechanism successfully conquers the dilemma in mix-signal VLSI testing. This thesis employs the TSMC 0.35μm 2p4m process, and use 3.3V power supply to implement the design. In this thesis we use Wilson current mirror (WCM) structure to design the current memories. By extending WCM into a differential pair, we design sensing amplifier, which have high-speed, high sensitive and micro-power (0.164mW) characteristics. Then, we further extend it into three applications including operational amplifier(bandwidth = 3.6MHz, loading = 100pF, power dissipation = 0.54mW, THD = -46dB), highest and lowest threshold voltage testing units of floating gate transistors in flash memory, and MOS current mode logic. The threshold voltage testing unit improves testing efficiency and reduces power consumption when applies to flash memory transistor testing. For MOS current mode logic, we propose the dynamic WCM-based current mode logic (DyWCML) structure and apply the DyWCML structure to a 4-bit adder design Using the TSMC 0.18μm 1p6m process and 1.8V power supply, the adder achieves 1.5GHz operation frequency and consumes only 4.6mW, which is the most superior in state-of-art works.