Data Traffic Performance of an Integrated Circuit- and Packet-Switched Multiplex Structure.

New results are presented for data traffic performance in an integrated multiplex structure which includes circuit-switching for voice and packet-switching for data. The results are developed both through simulation and analysis, and show that excessive data queues and delays will build up under heavy loading conditions. These large data delays occur during periods of time when the voice traffic load through the multiplexer exceeds its statistical average. A variety of flow control mechanisms to reduce data packet delays are investigated. These mechanisms include control of voice bit rate, limitation of the data buffer, and combinations of voice rate and data buffer control. Simulations indicate that these flow control mechanisms are quite effective in improving system performance. A combination of data buffer limitation with data-queue-dependent voice rate control was the most effective flow control technique tested. (Author)