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On implementing a soft error hardening technique by using an automatic layout generator: case study
- Source :
- 11th-IEEE-International-On-Line-Testing-Symposium.; 11th-IEEE-International-On-Line-Testing-Symposium., Dec 2004, French Riviera, France. IEEE Computer Society, Los Alamitos, CA, USA, xv+326 p., pp.29-34, <10.1109/IOLTS.2005.45>
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Abstract
- ISBN: 0769524060<br />Soft error rates induced by cosmic radiation become unacceptable in future very deep sub-micron technologies. Many hardening techniques at different abstraction levels have been proposed to cope with increased soft error rates. Depending on the abstraction level some techniques need to modify the design at architecture, circuit and transistor level, others required the modification of the circuit layout or to use new defined cells within the circuit. In this paper an automatic layout generator is presented to complete the system design process being able to easily generate the hardened design layout, thus reducing the system design time. This work aims at presenting a case study of a complete soft error tolerant integrated circuit by using an automatic layout generator called Parrot Punch.
Details
- Database :
- OAIster
- Journal :
- 11th-IEEE-International-On-Line-Testing-Symposium.; 11th-IEEE-International-On-Line-Testing-Symposium., Dec 2004, French Riviera, France. IEEE Computer Society, Los Alamitos, CA, USA, xv+326 p., pp.29-34, <10.1109/IOLTS.2005.45>
- Notes :
- French Riviera, France, 11th-IEEE-International-On-Line-Testing-Symposium., English
- Publication Type :
- Electronic Resource
- Accession number :
- edsoai.ocn892986975
- Document Type :
- Electronic Resource