A Simulation framework for hierarchical Network-on-Chip systems

Today, even the simplest laptop processor has at least four cores and a graphics card containing tens of cores. It is not hard to find more performance- oriented processors with hundreds of cores, and it is expected to see processors with thousands of cores in the not very far future. In these and future processors, the design of the interconnection network between the cores and the memory subsystem is a key design aspect. Simple topologies like buses or rings provide great e fficiency, but do not scale as good as meshes once the number of cores increases. We explore the use of hierarchical network designs as an alternative, where diff erent topologies are stacked in a single network. The lowest layers use rings or buses, taking advantage of locality, while other layers use meshes or more complex topologies. To fully explore these and other chip multiprocessor design aspects, we build an interconnection network simulator that is capable of simulating arbitrary hierarchies of multiple network topologies. We propose using parameterizable automata as tra ffic sources, as a trade-off between full processor simulation and simulation using purely random traffic. By altering the automaton high-level parameters, changes in the processor workload can be simulated, such as the expected average memory tra ffic, the locality of the memory accesses, the additional traffi c caused by diff erent cache coherency protocols, etc.