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Combining dynamic concurrency throttling with voltage and frequency scaling on task-based programming models

Authors :
Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Barcelona Supercomputing Center
Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
Navarro Muñoz, Antoni
Lorenzon, Arthur F.
Ayguadé Parra, Eduard
Beltran Querol, Vicenç
Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Barcelona Supercomputing Center
Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
Navarro Muñoz, Antoni
Lorenzon, Arthur F.
Ayguadé Parra, Eduard
Beltran Querol, Vicenç
Publication Year :
2021

Abstract

Being on the verge of exascale performance has shifted the prioritization of performance in applications to the inclusion of power-performance efficiency as a primary objective in the High Performance Computing (HPC) community. Simultaneously, this has surfaced hardware and software efforts that employ techniques such as dynamic voltage and frequency scaling (DVFS) for core and uncore units or dynamic concurrency throttling (DCT) to exploit hardware resources efficiently, by saving energy while maintaining performance. These techniques are complementary, so they can be used together. However, employing them is not a straightforward task, as they have to be adjusted based on the workload, and it is even more complex to combine them properly. Thus, these techniques should be applied transparently by a runtime system, without relying on application developers. In this paper, we extend a task-based runtime system with an infrastructure that categorizes workloads based on their computational profile – memory-bounded, compute-bounded, or balanced. This categorization is done in an on-line manner and with a negligible overhead. With this additional information, we enhance the CPU-manager and scheduler of OmpSs-2, a task-based parallel programming model, to automatically combine DVFS and DCT techniques based on workloads. Moreover, we show that our heuristics transparently improve energy efficiency on average by 15% with no significant performance loss and either equal or surpass the energy efficiency of the best static configuration available.<br />This research has received funding from the European Union’s Horizon 2020/EuroHPC research and innovation programme under grant agreement N.955606 (DEEP-SEA), and is supported by the Spanish State Research Agency - Ministry of Science and Innovation (contract PID2019-107255GB), and by the Generalitat de Catalunya (2017-SGR-1414). This work was also supported by Project HPC- EUROPA3, with the support of the EC Research Innovation Action under the H2020 Programme.<br />Peer Reviewed<br />Postprint (author's final draft)

Details

Database :
OAIster
Notes :
11 p., application/pdf, English
Publication Type :
Electronic Resource
Accession number :
edsoai.on1280135184
Document Type :
Electronic Resource