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Failure quantitative assessment approach to MOSFET power device by detecting parasitic parameters

Authors :
Yun, Minghui (author)
Yang, Daoguo (author)
He, Siliang (author)
Cai, Miao (author)
Xiao, Jing (author)
Zhang, Kailin (author)
Zhang, Kouchi (author)
Yun, Minghui (author)
Yang, Daoguo (author)
He, Siliang (author)
Cai, Miao (author)
Xiao, Jing (author)
Zhang, Kailin (author)
Zhang, Kouchi (author)
Publication Year :
2022

Abstract

With the emerging wide bandgap (WBG) semiconductor development, the increasing power density and efficiency of power electronic converters may cause more switching oscillation, electromagnetic interference noise, and additional power loss, further increasing the probability of device failure. Therefore, determining and quantifying the failure of a metal-oxide-semiconductor-field-effect transistor (MOSFET), which assembled using WBG semiconductor in some applications, is crucial to improving the reliability of a power converter. This study proposes a novel failure quantitative assessment approach based on MOSFET parasitic parameters. According to the two-port network theory, MOSFET is equivalent to some second-order RLC circuits composed of independent inductances, capacitances, and resistances in series. Then, the frequency-domain impedance associated with the physical failure of MOSFET is identified through frequency domain reflectometry. Accelerated aging and bond wires cut-off experiments are employed to obtain various quality states of the MOSFET device. Result shows that the MOSFET quality level and its number of bond wire lift-offs can be quantified effectively. Drain-to-source on-resistance (RDS(on)) that normally represents the MOSFET quality shows a positive linear function relationship on drain-to-source parasitic resistance (RD + RS) during the quality degradation proceeding. This finding matches with the correlation established between RDS (on) and RD + RS in theory. Meanwhile, source parasitic inductance (LS) increases with the severity of bond wires faults, and even the slight fault shows a high sensitivity. The proposed approach would be an effective quality screening technology for power semiconductor devices without power on treatment, which can effectively avoid the impact of junction temperature and test conditions (current and voltage) on test results, and does not ne<br />Electronic Components, Technology and Materials

Details

Database :
OAIster
Notes :
English
Publication Type :
Electronic Resource
Accession number :
edsoai.on1357881230
Document Type :
Electronic Resource
Full Text :
https://doi.org/10.3389.fphy.2022.1050678