Effect of interlayer trapping and detrapping on the determination of interface state densities on high-k dielectric stacks

© 2010 American Institute of Physics. The study was partially supported by the local government Junta de Castilla y León under Grant No. VA018A06, and by the Spanish TEC2007 under Grant No. 63318 and TEC2008 under Grant No. 06988-C02-O2.
The influence of the silicon nitride blocking layer thickness on the interface state densities (D(it)) of HfO(2)/SiN(x):H gate-stacks on n-type silicon have been analyzed. The blocking layer consisted of 3 to 7 nm thick silicon nitride films directly grown on the silicon substrates by electron-cyclotron-resonance assisted chemical-vapor-deposition. Afterwards, 12 nm thick hafnium oxide films were deposited by high-pressure reactive sputtering. Interface state densities were determined by deep-level transient spectroscopy (DLTS) and by the high and low frequency capacitance-voltage (HLCV) method. The HLCV measurements provide interface trap densities in the range of 10(11) cm(-2) eV(-1) for all the samples. However, a significant increase in about two orders of magnitude was obtained by DLTS for the thinnest silicon nitride barrier layers. In this work we probe that this increase is an artifact due to the effect of traps located at the internal interface existing between the HfO(2) and SiN(x):H films. Because charge trapping and discharging are tunneling assisted, these traps are more easily charged or discharged as lower the distance from this interface to the substrate, that is, as thinner the SiN(x):H blocking layer. The trapping/detrapping mechanisms increase the amplitude of the capacitance transient and, in consequence, the DLTS signal that have contributions not only from the insulator/substrate interface states but also from the HfO(2)/SiN(x):H interlayer traps.
Junta de Castilla y León
Spanish TEC2007
Spanish TEC2008
Depto. de Estructura de la Materia, Física Térmica y Electrónica
Fac. de Ciencias Físicas
TRUE
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