Tracking Multicore Contention in Memory Controllers and DRAM

The main memory subsystem has traditionally been one of the more complex resources to analyze in multicore real-time embedded systems, with memory controller considerations and JEDEC timing constraints being the more prominent factors contributing to such complexity. One of the main challenges in multicore real-time systems is the production of the necessary evidence regarding the management of contention for the certification of multicore platforms in safety-relevant sectors. As current MPSoC platforms provide little information on how tasks may be interacting and delaying each other at large, it still remains a tall order to provide evidence about the correctness of hardware and software mechanisms deployed specifically to mitigate and manage contention on shared resources. This work attempts to bridge this gap by proposing a low-overhead hardware mechanism to tightly track inter-core contention within the main memory subsystem. The proposed technique enhances the quality of timing- and contention-related evidence, increasing the explainability and management of multicore contention in the main memory subsystem for multicore real-time systems in relation to applicable safety standards regulating their usage.