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This paper discusses the stuck bits induced by the gate breakdown of PMOS in the sub-20 nm FinFET static random access memory (SRAM) device. After the heavy-ion experiment, several stuck bits are in the FinFET SRAM matrix, which cannot be set or reset. To investigate the factors that caused the stuck bit, we perform the electrical failure analysis (EFA) to measure the electric characteristics of the transistors in the stuck bits and normal cells separately. The measurement results show a clear gate breakdown at the PMOS pull-up (PPU) transistor in all of the measured SRAM cells. Meanwhile, the SPICE simulation based on the EFA results verifies the impact of the damaged PPU. Finally, considering all of the phenomena, the charge deposition from single events is the major mechanism that causes the stuck bits in FinFET SRAM. The experiment results alert a potential gate breakdown risk in the ultra-high-density FinFET SRAM applied in the space environment. [ABSTRACT FROM AUTHOR]

InGaN-based micro-light-emitting diodes (LEDs) grown on Si have gained tremendous interest for full-color displays. Strain management is a key challenge for the epitaxial growth of InGaN-based long-wavelength LEDs on Si because the accumulated compressive strain can severely limit In incorporation and degrade the quality of InGaN multi-quantum wells (MQWs) when the conventional Al-composition step-graded AlN/AlGaN buffer is used for strain control. In this work, we demonstrate a promising approach to effectively reduce the in-plane residual compressive stress of GaN by using an AlN single-layer buffer. The in-plane lattice parameter of the GaN underlayer was increased from 3.183 to 3.189 Å with the residual compressive stress at room temperature reduced from 0.37 to ∼0 GPa, which significantly improved the In incorporation of InGaN MQWs and extended the photoluminescence wavelength from 510 to 550 nm. A remarkably high internal quantum efficiency of 78% was thus achieved for the as-grown InGaN-based green LEDs on Si. This work paves the way for the growth of high-efficiency InGaN-based long-wavelength micro-LEDs. [ABSTRACT FROM AUTHOR]

In this work, AlN polarization-enhancement interlayer (AlN-PEL) is adopted to enhance two-dimensional hole gas (2DHG) density in a p-GaN/AlN-PEL(∼2 nm)/AlGaN(<6 nm)/GaN heterostructure, aiming at monolithic integration of p/n-channel field effect transistors (p-FETs) on GaN-on-Si substrate. Owing to the strong built-in polarization of the AlN-PEL, high density 2DHG over 2.3 × 1013 cm−2 with good immunity to thermal freeze out effect is realized. Assisted by a two-step gate trench etching process, enhancement-mode (E-mode) buried-channel GaN p-FETs with temperature independent ON-resistance RON, and ON/OFF current ratio ION/IOFF (>108), have been fabricated. The fabricated p-FETs also deliver thermally stable subthreshold swing as well as threshold voltage Vth, and smaller Vth shift than that of p-FETs without the AlN-PEL, which is primarily due to enhanced 2DHG confinement by the AlN-PEL. The proposed structure is an attractive platform for monolithic integration of GaN-based logic and power devices for cryogenic applications as low as 10 K. [ABSTRACT FROM AUTHOR]

A HfO2/Al2O3/AlN stack deposited in a plasma-enhanced atomic layer deposition system is used as the gate dielectric for GaN metal–insulator–semiconductor structures. Prior to the deposition, in situ remote plasma pretreatments (RPPs) with O2, NH3, and NH3–O2 (in sequence) were carried out. Frequency-dependent capacitance–voltage (C–V) measurements reveal that for all the RPP-treated samples, the interface trap density Dit was significantly reduced compared to the sample without RPP. In particular, the NH3-treated sample exhibits an extremely low Dit of ∼1011 cm−2·eV−1 from EC − 0.31 eV to EC − 0.46 eV. To characterize the interface traps at deeper levels, the transfer pulsed I–V measurement was employed further. In the energy range of EC − ET > 0.54 eV, the interface trap charge density Qit of various samples demonstrates the following order: NH3 RPP < NH3–O2 RPP < O2 RPP < without RPP. By adjusting multiple pulse widths, the Dit derived from the Qit result matches the C–V measurement precisely. Moreover, X-ray photoelectron spectroscopy analysis of the Ga 3d core-level indicates that NH3 RPP facilitates the conversion of Ga2O into GaN at high RF power of 2500 W, whereas O2 RPP mainly oxidizes GaN to relatively stable Ga2O3. Combined with the C–V and pulsed I–V measurements, it is confirmed that a strong positive correlation exists between Ga2O and the interface traps, rather than Ga2O3. [ABSTRACT FROM AUTHOR]

This Letter reports low-temperature (700 °C) growth of heavily Si-doped GaN (n++GaN) by metal-organic chemical vapor deposition with a resistivity as low as 1.9 × 10−4 Ω·cm and an atomically smooth surface. Indium adatoms added during the growth of n++GaN play an important role in improving both the surface morphology and free electron concentration. On the one hand, acting as surfactant, they greatly boost the adatoms surface mobility at low growth temperature and mitigate Si-induced anti-surfactant effect. On the other hand, they can effectively suppress the formation of compensating defects, thus contributing to an extremely high electron concentration of 2.8 × 1020 cm−3. This high-quality n++GaN was further applied to the realization of Ohmic contacts with an ultra-low contact resistance for AlGaN/GaN high electron mobility transistors. The carrier gas was carefully modulated for the selective area epitaxy (SAE) of n++GaN to facilitate the nucleation of GaN on the dielectric mask, which effectively suppressed the undesired mass transport and resulted in a uniform SAE of n++GaN in the recessed source/drain regions. A nearly defect-free interface between the n++GaN and two-dimensional electron gas channel has been also realized, and the resistance induced by the interface was only 0.03 Ω·mm. As a result, an ultra-low contact resistance of 0.07 Ω·mm has been realized. This work lays a solid foundation for further improving the performance of GaN-based RF and power devices. [ABSTRACT FROM AUTHOR]

This article was originally published online on 27 December 2023 with an error in the affiliation. The affiliation appears correct above. All online versions of this article were corrected on 4 April 2024.By Yingjie Wang; Sen Huang; Qimeng Jiang; Xinhua Wang; Zhongchen Ji; Jie Fan; Haibo Yin; Ke Wei; Xinyu Liu; Qian Sun and Kevin J. ChenReported by Author; Author; Author; Author; Author; Author; Author; Author; Author; Author; Author [Extracted from the article]