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This paper studies an $H_{\infty }$ model reduction problem for interval frequency negative imaginary (IFNI) systems. For a given IFNI system, our goal is to find a reduced-order IFNI system satisfying a pre-specified $H_{\infty }$ approximation error bound over the finite-frequency interval. Necessary and sufficient conditions in terms of matrix inequalities are derived for the existence and construction of an $H_{\infty }$ reduced-order IFNI system. An improved iterative algorithm is provided to solve the matrix inequalities and to minimize the $H_{\infty }$ approximation error. The proposed method is further clarified via the application to the electrical circuits, such as high-order Sallen–Key low-pass filter, piezoelectric tube scanner, and RLC circuit. The simulation results on these electrical circuits are compared with the finite-frequency interval Gramians-based model reduction method both in the frequency domain and time domain. [ABSTRACT FROM AUTHOR]

A novel nonlinear filter, which incorporates the concept of exponential sinusoidal models into nonlinear filters based on functional link networks (FLNs) has been developed in this paper. The proposed filter is designed to provide improved convergence characteristics over traditional FLN filters. The conventional trigonometric FLN may be considered as a special case of the proposed adaptive exponential FLN (AEFLN). An adaptive exponential least mean square (AELMS) algorithm has been derived and the same has been successfully applied for identification of a couple of nonlinear plants. The AEFLN-based nonlinear active noise control (ANC) system has also been designed and an adaptive exponential filtered-s least mean square (AEFsLMS) algorithm has been developed to update the weights as well as the exponential factor. Simulation study has revealed the improved noise mitigation offered by the AEFLN-based nonlinear ANC system. [ABSTRACT FROM AUTHOR]

This paper presents a systematic approach for the statistical simulation of nonlinear networks with uncertain circuit elements. The proposed technique is based on spectral expansions of the elements' constitutive equations (I-V characteristics) into polynomial chaos series and applies to arbitrary circuit components, both linear and nonlinear. By application of a stochastic Galerkin method, the stochastic problem is cast in terms of an augmented set of deterministic constitutive equations relating the voltage and current spectral coefficients. These new equations are given a circuit interpretation in terms of equivalent models that can be readily implemented in SPICE-type simulators, as such allowing to take full advantage of existing algorithms and available built-in models for complex devices, like diodes and MOSFETs. The pertinent statistical information of the entire nonlinear network is retrieved via a single simulation. This approach is both accurate and efficient with respect to traditional techniques, such as Monte Carlo sampling. Application examples, including the analysis of a diode rectifier, a CMOS logic gate and a low-noise amplifier, validate the methodology and conclude the paper. [ABSTRACT FROM AUTHOR]

This paper presents an event-driven simulation methodology for injection-locked oscillators. The proposed method adopts a phase-domain macromodel based on a perturbation projection vector (PPV), which expresses the oscillator's phase response using a nonlinear, time-varying differential equation. By expressing the PPV using a piecewise polynomial function, the PPV model can be simulated in an event-driven fashion on a digital logic simulator like SystemVerilog. While this piecewise polynomial approximation introduces a trade-off between the simulation accuracy and speed, our results show that the simulation accuracy quickly reaches its optimal value as the piecewise interval number increases even with first-order polynomials. The experimental results with an LC oscillator, ring oscillator, and burst-mode CDR models operating with both periodic and aperiodic inputs demonstrate that the proposed models achieve speeds up to 2\sim 30\times that of transistor-level Spectre simulations with the same accuracy. [ABSTRACT FROM PUBLISHER]

The paper describes the impact of time-delays on small-signal angle stability of power systems. With this aim, the paper presents a power system model based on delay differential algebraic equations (DDAE) and describes a general technique for computing the spectrum of DDAE. The paper focuses in particular on delays due to the terminal voltage measurements and transducers of automatic voltage regulators and power system stabilizers of synchronous machines. The proposed technique is applied to a benchmark system, namely the IEEE 14-bus test system, as well as to a real-world system. Time domain simulations are also presented to confirm the results of the DDAE spectral analysis. [ABSTRACT FROM AUTHOR]

Sub-harmonic pulse injection-locked oscillators are becoming attractive candidates for the design of clock multipliers and as building blocks of phase-locked loops. Unfortunately, due to the large amplitude of the injected signals, these circuits cannot be analyzed with conventional methods and very-time-consuming simulations are needed to determine their phase noise performance. Phase-noise simulations are particularly critical when the ratio N between the output and the injection frequency gets large. To address the above issue, this paper provides an efficient computation flow to derive the phase noise of pulse injection-locked oscillators. The flow simply requires the computation of the phase-domain response and the phase noise of the free-running oscillator. An analytical expression, herewith demonstrated and compared against commercial simulation tools, allows calculating the phase noise of the injection-locked oscillator for any frequency ratio N. [ABSTRACT FROM AUTHOR]

This paper presents new design procedure for a general class-E power amplifier, here referred to as quasi-class-E, with finite dc-feed inductance and switch on-resistance and variable duty cycle under variable voltage switching (VVS), and variable derivative voltage switching (VDS), taking into account the switch breakdown voltage. It is shown that for non-zero switch on-resistance in class-E power amplifier, zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions do not necessarily result in maximum efficiency. Hence, by assuming VVS and VDS, new design equations are derived. The new equations can be solved with a simple and fast numerical method in MATLAB. The theoretical results show efficiency improvement for quasi-class-E power amplifier compared to conventional designs. Circuit simulations confirm the validity of the theoretical results. [ABSTRACT FROM AUTHOR]

This paper describes an accurate, yet analytical method to predict the key characteristics of a bang-bang controlled timing loop: namely, the jitter transfer (JTRAN), jitter generation (JG), and jitter tolerance (JTOL). The analysis basically derives a linearized model of the system, where the bang-bang phase detector is modeled as a set of two linearized gain elements and an additive white noise source. This phase detector (PD) model is by far the most extensive one in literature, which can correctly estimate the effects of random jitter, transition density, and finite loop latency on the loop characteristics. The described pseudo-linear analysis assumes the presence of random jitter at the PD input and the minimum jitter necessary to keep the linear model valid is derived, based on a describing function analysis and Nyquist stability analysis. The presented analysis re-confirms the findings of prior theories and provides theoretical basis to the prior empirically-drawn equations, such as those for the quantization noise power and the gain reduction in presence of a finite loop delay. The predictions based on the presented analysis match well with the results from time-accurate behavioral simulations. [ABSTRACT FROM PUBLISHER]

While a host of analysis techniques exist to perform steady-state analysis of open-loop converter systems, solutions for close-loop converter systems are distinctly more challenging to obtain. Analysis is done either via computationally intensive time-domain simulation or through reliance on a disconnected collection of published iteration techniques. Moreover, most of these iteration techniques deal with a system containing only one or two converters. This is not adequate to deal with a smart grid or microgrid system, which consists of multiple (more than two) converters. This paper proposes a generalized and systematic solution procedure to obtain the steady state of a system containing multiple closed-loop power converters, in a computationally efficient manner. The solution procedure consists of a general five step approach that can easily be applied to a wide variety of power converter systems. It is shown that numerous previously proposed methods may be viewed as specific implementations of the generalized systematic procedure. A new solution approach, suitable for analysis of tightly coupled multiconverter networks, is developed based on the generalized solution procedure. Results of the new approach are validated against PSCAD/EMTDC simulations for a representative multiconverter network. [ABSTRACT FROM PUBLISHER]

This paper presents a design-oriented analytical approach for predicting fast-scale instability in power electronics converters under voltage-mode control strategy. This approach is based on the use of the ripple amplitude of the feedback control voltage as an index for predicting subharmonic oscillations in these systems. First, the work revisits the stability analysis technique based on the nonlinear discrete-time model, demonstrating that the ripple amplitude can be included within the expression of the Jacobian matrix of this model, hence giving a mathematical support to extend the ripple index to more complex topologies. A simple but representative buck converter under voltage-mode control is used to illustrate the approach. Using the ripple-based index, closed-form expressions of stability boundaries are derived. Unlike other available results obtained from existing methods, the stability boundary, in this work is expressed analytically in terms of both power stage and controller design parameters. Moreover, one can determine how these parameters are involved in the closed form expressions and, furthermore, how each parameter affects the stability of the system. The approach is validated by numerical simulations from the state equations and also experimentally within a wide range of the design parameter space. [ABSTRACT FROM PUBLISHER]

Accurate distortion modeling of feedback amplifier with Miller compensation is the main subject of this paper. Inspired by traditional Rosenstark method, a nonlinear signal-flow-based method has been developed. Based on the proposed method, the nonlinear coefficients of each gain stage can be evaluated exactly and the rules of cascading, feedback can be found conveniently. As a result, the second- and third-order harmonic distortion factors are obtained in a simple manner. The application range includes all kinds of Miller compensation strategies with or without feedforward compensation path. The distortion modeling of a two-stage opamp compensated with Miller capacitor and nulling resistor is used to show versatility of the proposed method. In addition, simplified distortion factor expressions, approximate characteristic frequencies of the distortion factors and the value of external configuration resistors for canceling the second-order harmonic components at DC are also derived and can be used to accelerate distortion evaluation of opamp designs. Accuracy of the method was verified by comparing the results between theoretical analysis and transistor level simulation. [ABSTRACT FROM AUTHOR]

Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-N PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL. [ABSTRACT FROM PUBLISHER]

In this paper, a new VLSI implementable Hopf oscillator with dynamic plasticity is proposed for next-generation portable signal processing application. A circuit-realizable piece-wise linear function has been used to govern the frequency adaptation characteristic of the proposed oscillator. Furthermore, a straightforward method is suggested to extract the frequency component of the input signal. Mathematical model of the oscillator is derived and it is shown, using VHDL-AMS model, that despite using a new nonlinear function, the oscillator exhibits the same characteristics and learning behavior as the original one with improved learning time. Subsequently, an equivalent circuit model and transistor level implementation for the oscillator is suggested and the mathematical model is confirmed with system and circuit level simulations. Capability of such oscillator to extract frequency futures without doing explicit signal processing is shown with examples of both synthetic and real-life EMG signals. [ABSTRACT FROM PUBLISHER]

This paper presents a capacitor mismatch calibration technique in multibit discrete-time sigma-delta (\Sigma \Delta) modulators based on a capacitor error model, including nonideal integrator gain errors. This model enables the compensation of mismatch-induced nonlinear memory errors in conversion using a simple finite-impulse-response structure. Single-bit pseudorandom noise (PN) is utilized to identify the error coefficients, and an analog-domain PN removal technique is devised to minimize the input signal dynamic-range loss due to the PN circulation in the \Sigma \Delta loop. The behavioral simulation demonstrates that the proposed scheme effectively compensates for the multibit capacitor mismatch errors in the first- and second-order \Sigma \Delta modulators. [ABSTRACT FROM PUBLISHER]

Type-II charge-pump (CP) phase-locked loop (PLLs) are used extensively in electronic systems for frequency synthesis. Recently, a passive sampled loop filter (SLF) has been shown to offer major benefits over the conventional continuous-time loop filter traditionally used in such PLLs. These benefits include greatly enhanced reference spur suppression, elimination of CP pulse-position modulation nonlinearity, and, in the case of phase noise cancelling fractional-N PLLs, improved phase noise cancellation. The main disadvantage of the SLF to date has been the lack of a linear time-invariant (LTI) model with which to perform the system-level design of SLF-based PLLs. Without such a model, designers are forced to rely on trial and error iteration supported by lengthy transient simulations. This paper presents an accurate LTI model of SLF-based type-II PLLs that eliminates this disadvantage. [ABSTRACT FROM PUBLISHER]

Traditional power-system dynamic simulation tools make a number of simplifying assumptions to speed up computations; thus, they can only capture snapshots of the system operation, ignoring the dynamics between states. This paper applies the shifted-frequency-analysis (SFA) theory to the Electromagnetic Transients Program (EMTP) simulator in order to efficiently obtain the time-domain simulation results in the neighborhood of the fundamental frequency without making quasi-steady-state or other simplifying assumptions. The SFA-based EMTP simulator can provide dynamic-phasor results that accurately trace the evolution of the system state in three-phase power systems. Dynamic phasors provide envelopes of the time-domain waveforms and can be accurately transformed back to instantaneous time values. Test cases have verified the usefulness of the SFA-based dynamic simulation method. [ABSTRACT FROM PUBLISHER]

A new paradigm for the analysis of super-regenerative (SR) receivers is proposed. Unlike the methodology used in the past where alternately stable and unstable modes of operation are considered, this approach models the system as a stable filter with modulators at the input and output. Consequently, the behavior of SR systems can be viewed using steady state techniques as opposed to time-varying transient analysis. The basic mathematical result derived using this paradigm is compared to the currently accepted solution in the literature and is found to be essentially the same. Then, using state space techniques this solution is modified to obtain newly derived results for the envelope solution, where the resulting down-conversion enables an extremely efficient simulation approach. Finally, the paradigm is extended to show that with the addition of frequency modulation, an even more accurate closed form solution to the problem is available. Simulation results are offered which validate the analysis. [ABSTRACT FROM PUBLISHER]

A novel electrical circuit spiking neuron model that has a piece-wise-constant vector field with a state-dependent reset is presented. It is shown that the model exhibits six kinds of border-collision bifurcations, where their bifurcation sets are derived and are summarized into two parameter diagrams. Then, using the diagrams, systematic synthesis procedures of the presented model so that it can reproduce four kinds of bifurcation scenarios that are typically observed in standard neuron models are presented. It is shown that the model can reproduce the bifurcation scenarios as well as corresponding nonlinear response characteristics observed in model and biological neurons. Occurrences of typical neuron-like bifurcations are confirmed by experimental measurements. [ABSTRACT FROM PUBLISHER]

A fast simulation method for time-derivative cellular neural networks (TDCNN) is proposed. Using forward Euler approximation (FEA) for the derivative of the cell state and the backward Euler approximation (BEA) for the derivatives of the neighboring cell states enables the recursive computation of the cell state and provides a speed advantage of orders of magnitude. The state equations are then packed into a vector-matrix form which enables the previously empirically given time constraint to be expressed as a matrix condition. It is shown that using both FEA and BEA leads to a second-order difference equation whose corresponding second-order differential equation is derived and shown to yield the same simulation results. [ABSTRACT FROM PUBLISHER]

A memristor emulator which imitates the behavior of a \ TiO2 memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp∼\ TiO2 memristor model in real circuit. [ABSTRACT FROM AUTHOR]

A new adaptive circuit design approach is proposed and analyzed employing independently biased back-gated Double-Gate MOSFET (DGMOSFET) devices. Threshold voltage tuning using back-gate of the DGMOSFET was compared with a conventional body-bias method. The technique is a promising solution to control the transistor's threshold voltage while reducing undesirable effects at the sub-50-nm device technology nodes. An automatic adaptive circuit for threshold voltage tuning was implemented using DGMOSFET devices in 45 nm CMOS technology. Simulation results show that this circuit compensates for static and dynamic variations. This adaptation approach using DGMOSFETs along with adaptive supply voltage scaling allows simultaneous optimization of power and performance according to application-specific workload and requirements. Simulation results using a 45 nm CMOS technology indicate that this adaptive circuit design can provide 50% higher performance for the same energy, or consume 40% less energy for the same performance. In contrast to conventional methods which only employ dynamic voltage scaling, adaptive tuning of threshold voltages reduces power consumption while maintaining its noise margin. [ABSTRACT FROM AUTHOR]