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This paper describes the modeling and design of package-embedded magnetic-core inductors for a system-in-package-based high-efficiency integrated voltage regulator. An application example is used to demonstrate the complete design process, starting with the fabrication of two candidate magnetic composite materials. Based on the measured properties of these materials, magnetic-core inductors are designed and simulated using full-wave simulations. Finally, the overall voltage regulator efficiencies resulting from inductor designs are obtained from analytical equations, which allows for rapid evaluation of different scenarios. Voltage regulator efficiency with magnetic-core inductors is seen to be considerably higher than with similarly sized air-core inductors. Notably, this is even true at high switching frequencies where the magnetic-core inductors have lower quality factors than the air-core inductor. [ABSTRACT FROM AUTHOR]

This paper deals with the study of technologies for flip-chip assembly of CMOS integrated power converters on standard FR4 organic substrates. Tests for the characterization of commercially available technologies for microassemblies, such as anisotropic adhesive bonding, thermocompression bonding, thermosonic/ultrasonic bonding, and solder bonding, are carried out. The aim of this paper is to determine the most suitable flip-chip bonding technology for power CMOS circuits with more than 50 pads. First, the coupled design of the CMOS chip and the corresponding substrate dedicated to low-power microconversion (10 W) is presented. It is shown that the parasitic resistances and inductances of the interconnections increase the conduction and switching losses of the device. This leads to a temperature rise, which can limit the operating ratings of the circuit. The experimental results are provided to evaluate each technology for flip-chip assembly. [ABSTRACT FROM PUBLISHER]

This paper presents a lumped dynamic electrothermal model of an insulated gate bipolar transistor module of inverters. The thermal model consists of a 3-D network of $RC$ cells constructed for time-dependent operation. The network was found to be precise for determining the temperature excursion of diodes and transistors subsequent to time-dependent power losses. Thermal resistances and capacitances accounting for heat spreading and thermal penetration depth effects were introduced. Electrothermal simulations carried out on a 1200 V–300 A module with a time-dependent average power loss were found to be in good agreement with experiments using infrared thermal imaging. This paper focuses on very-low-frequency behavior (less than 1 Hz) at a switching frequency of 10 kHz. [ABSTRACT FROM AUTHOR]

In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise. That causes the voltage to drop and also to oscillate at the power delivery network’s resonance frequency. This power supply noise causes clock jitter. The voltage-controlled oscillator of the proposed PLL is designed at 45-nm technology such that when there is supply voltage variation, it is automatically corrected by a feedback methodology having only 11-ps response time delay, compared to 588-ps clock period. Simulation result shows that, for the proposed new PLL design, the number of places where the clock periods are altered due to this power supply voltage fluctuation is reduced. The performance of the proposed PLL design in terms of reduction of clock jitter, caused by the variation of power supply voltage and the flatness of the frequency versus power supply voltages, is tested by feeding the clock to a circuit (c17 of ISCAS’85) for the conventional methodology and also for our new methodology. It has been shown that, using the proposed method, the clock jitter caused by the power supply noise can be reduced by about 50% compared to the conventional design methodology. [ABSTRACT FROM AUTHOR]

A tunable bandstop filter (BSF) with a wideband balun using integrated passive devices (IPDs) technology for multichip module is proposed. The compact tunable BSF uses barium strontium titanate (BST) varactors demonstrating a tuning range of 55% from 1.3 to 2.3 GHz with a 20-dB rejection level. The performance of the filter is optimized by applying asynchronous biases to the BST varactors, leading to bandwidth and rejection level improvement. High-power test results show that the filter exhibits a third-order input intercept point of more than 40 dBm. An IPD wideband balun (0.5–2.5 GHz with ±1 dB amplitude imbalance and 180° ± 20°) using a wideband phase inverter is also presented. The design considerations of the wideband phase inverter (1.5–8 GHz) are addressed in this paper. Design and measured results are also presented for a fixed IPD bandpass filter, and an IPD bandpass filter with a tunable transmission zero to demonstrate the reconfigurability in frequency agile applications. [ABSTRACT FROM AUTHOR]

Power conversion applications in the low voltage (LV) range (≤ 1.2 kV)—such as three-phase inverters—are required to operate at higher efficiencies, higher ambient temperatures, increasingly smaller form factor, and higher power density. Up to now, most research has focused on voltages up to 650 V for printed circuit board (PCB) embedded power electronics. This research evaluates a novel three-phase invertor module based on six insulated gate bipolar transistors and six diodes rated to 1.2 kV and 25 A each. This unique module is compared to the Semikron MiniSKiiP 23AC126V1. This paper considers some key details of the PCB embedding assembly process, a comparative switching performance assessment, measurement of thermal resistance, comparative lifetime, and electric insulation. First, a detailed outline of the package is presented including the top- and bottom-side metallization and the copper interconnect technology. The switching performances of both modules are compared for turn-ON and turn-OFF currents for a waveform at 600 V and 25 A at 150 °C. A finite-element-method thermal simulation demonstrates up to 44% lower thermal resistance for the PCB embedded package than that of the traditional wire-bonded direct bonded copper (DBC) package for an identical applied current and cooling condition. Furthermore, both packages are active power cycled to failure with the PCB embedded package demonstrating superior lifetime to the traditional DBC module. Finally, the maximum breakdown limit and the onset of partial discharge with the embedded PCB module are reported for both aged and non-aged conditions. The overall findings identify the promising application of PCB embedded power electronics for LV power conversion. [ABSTRACT FROM PUBLISHER]