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This paper addresses the problem of fast transient simulation of high-speed coupled channels driven by transceivers that include transmitter feed-forward equalization (TX-FFE). Practical circuit hardware implementations of such drivers may not be correctly represented by industry-standard algorithmic modeling interfaces (AMIs), which are usually based on ideal digital finite impulse response filters. In particular, slow transients may arise when aggressive FFE is activated and particular switching sequences significantly stress local voltage regulators integrated in the output buffers. In this paper, we model this effect using a constructive hierarchical approximation of the analog waveforms that form a linearized vector Thevenin or Norton representation of the driver. This representation enables the accurate simulation of coupled channels including both differential- and common-mode signals. Analog waveforms at the receiver input are readily obtained by standard time-frequency transformations while including channel characteristics and any additional linear equalization block, if present. This proposed framework is compatible with industry-standard AMIs, extending their scope to coupled channels with nonideal TX-FFE circuit blocks. Eye diagrams and transient waveforms corresponding to millions of bits are computed in few seconds using a nonoptimized software implementation. Random jitter and crosstalk are seemlessly included as in standard AMI frameworks. The results of various numerical experiments on commercial transceivers are reported in this paper, confirming both the accuracy and the efficiency of the proposed framework. [ABSTRACT FROM AUTHOR]

The abnormal rise in contact temperature in switchgear may lead to overheating or even explosion. It is necessary to monitor the rise in real contact temperature to ensure the safety and stability of switchgear. The accurate measurement of real contact temperature is still a problem, and the continuous state of switchgear cannot be assessed accurately by the temperature monitor. In this paper, a particular installation scheme of temperature sensor is put forward and a calculation algorithm for temperature rise of tulip contacts by the measured temperature of bus bar in real time based on artificial neural network (ANN) is established. An electromagnetic-thermal-fluid coupled simulation model for 10-kV/4000-A switchgears was built, and the thermal characteristic was studied taking the influential factors such as load current, ambient temperature, and contact resistance into consideration. The effectiveness of simulation model is discussed by the comparison to temperature rise experiment. Then, an ANN with three layers of structure is established to calculate the temperature of tulip contacts. The sensitivity and accuracy of network are calculated and verified. The results of this paper may provide a novel method for the monitor of switchgear temperature and assess continuous condition of high-current switchgear. [ABSTRACT FROM AUTHOR]

Radio frequency (RF) coaxial switches have the advantages of high transmission frequency and power capacity and are widely used in aerospace, communications, military, science, and medical fields. In accelerated thermal cycle (ATC) test, a permanent deformation or displacement occurs in the contact system of RF coaxial switch caused by creep and the RF performance downgrades with the thermal cycle times. In this paper, a 3-D finite-element model of an RF coaxial switch was first proposed. The power loss in the contact system when the switch transmits high frequency and power signals was divided into the conductor loss and the dielectric loss, which were calculated separately. It was noted that conductor loss was the main part of power loss. Then, the power loss in the contact system was considered as the heat source, and the steady-state temperature field of the whole switch was calculated with Ansoft HFSS and Workbench. The temperature rise in an RF coaxial switch was calculated and verified by experimental testing. In order to predict the reliability and working life of RF coaxial switch in ATC test, a creep constitutive equation based on the Coffin–Mason method that has three undetermined coefficients was built. According to ISO204:2009 (Metallic materials-Uniaxial creep testing in tension), the samples of beryllium bronze for creep testing were produced, and two groups of creep testing in the condition of different temperatures and stresses were carried out to obtain the undetermined coefficients. Finally, the stress–strain deformation of contact system with the thermal cycle times was calculated based on the creep constitutive equation. The model of contact system was rebuilt, and the influence of creep on RF coaxial switch in ATC test was investgated. The analysis methods and conclusions presented in this paper have important theoretical significance and practical value for improving the performance and reliability of RF coaxial switch products. [ABSTRACT FROM AUTHOR]

A microelectromechanical systems (MEMS) low-g inertial switch is typically used for linearly increased/decreased acceleration signal sensing. In this paper, we introduce a novel design concept of MEMS inertial switch based on direct contact sensing method to eliminate the bouncing effect of the output signal. The switch was designed with a threshold value of 12 g and composed by a proof mass, suspended by six Z-shaped flexure beams. The fabrication was carried out on a silicon-on-insulator (SOI) wafer with standard silicon micromachining. Two glass wafers were used to encapsulate the switch and establish a direct connection between the movable electrode and the detection circuits. According to the centrifugal experiment results, the measured threshold value is around 11.8 g, which is in good agreement with the designed value. The comparison of contact behavior between direct and indirect contact switches was also carried out. The results showed that the direct contact switch could eliminate the output signal bouncing effect, especially when the applied acceleration signal was approximate to the threshold value of the switch. [ABSTRACT FROM AUTHOR]

The class-E shunt inductor inverter (SII) topology typically operates based on zero-current switching (ZCS) and zero-derivative current switching (ZDCS) conditions. Based on these terms, the peak switch voltage and load resistance are eliminated as the major limitation parameters to implement the class-E SII with the desired design specifications. This paper introduces the design and analysis of the class-E SII with the specified deviation from both ZCS and ZDCS conditions. Therefore, 2 degrees of the design freedom are obtained. Two new parameters that are normalized by the dc-supply current are defined in terms of the deviation from ZCS, i.e., $\alpha $ and ZDCS, i.e., $\beta $. This operation mode of class-E SII is named as the nonzero current. The performance characteristics and design relationships are obtained in terms of the phase shift between the input and output voltages. The demonstration of the proposed operation mode is proven by fabrication of a prototype circuit with output power 10 W at 4-MHz operating frequency and close agreement between experimental outcomes with the simulation and theoretical results. [ABSTRACT FROM AUTHOR]

Arc chutes comprising ferromagnetic splitter plates are common in SF6-insulated medium-voltage switchgears. By splitting and cooling the electric arc, they help to interrupt moderate currents such as the rated current in load break switches or the transfer current in switch–fuse combinations. Between the splitter plates of such an arc chute, the motion of the arc depends on the balance of the attracting magnetic forces from the ferromagnetic plates, the repelling forces between two arc columns at the two sides of a plate, and the viscous forces from the insulating gas. We simulated this motion by calculating the magnetic forces acting on the arc columns after splitting by means of 2-D and 3-D electromagnetic finite-element analyses and by taking the viscous force as drag force into account. This paper describes this calculation method and compares the simulation results with those of laboratory tests. [ABSTRACT FROM AUTHOR]

This paper presents a new approach aiming at simulating the steady-state response of dc–dc switching power converters. The proposed method uses the main concept behind the harmonic balance (HB) to compute the amplitudes of the harmonic content in the steady-state waveform. The proposed approach extends the basic HB to enable its efficient implementation to the power converter circuits, through developing equivalent frequency-domain-based stamps for ideal switching elements. The new technique is formulated to yield, along with the amplitudes of the harmonics, the switching times in the ideal switching elements, resulting in the convergence of the Newton method being obtained within few iterations. A major advantage in the proposed method is that it enables removing the control circuitry, which reduces the size of the circuit and significantly contributes to the efficiency of the method. Experimental results show significant speedup over commercial SPICE-based simulators. [ABSTRACT FROM AUTHOR]

Contact erosion and dielectric strength reduction due to arc discharge are critical problems, particularly for dc switches and circuit breakers. Long-duration arcs not only cause serious contact erosion but also reduce the dielectric strength of the contact gap. A hybrid dc switch composed of a mechanical switch (MS) and a semiconductor device can drastically decrease the duration of the arc compared to a conventional MS. This paper aims to examine the influence of short-duration arcs on the contact erosion and dielectric strength in a hybrid dc switch. A dc current of up to 800 A is flown through copper contacts that are connected in parallel with a SiC-MOSFET. An arc discharge is formed between the contacts just after they are opened. Then, a pulsed high voltage is applied between the contacts to measure the breakdown strength of the contacts. A piezo actuator opens the contacts, which have a gap length of $300~\mu \text{m}$. When the dc current is increased from 200 to 800 A, the arc duration increases from 4 to $14~\mu \text{s}$ and causes surface erosion and lengthened protrusions. The contact resistance does not increase. However, the breakdown electric field is decreased. [ABSTRACT FROM AUTHOR]

Hybrid dc switches have become increasingly prominent due to their low ON-state energy loss and less arc erosion in comparison with conventional semiconductor and mechanical switches. Zero-voltage switching (ZVS) is a common method for realizing a hybrid dc switch. However, a certain amount of contact voltage rather than zero voltage is necessary for commutating the current into the semiconductor devices from the mechanical contacts, which may cause arc generation if the contact voltage exceeds the boiling voltage of the contact material. It has been found that current commutation can be accomplished without arc generation if the current is below a threshold value. It is important to determine and improve the threshold current of arc-less current commutation for suppressing arcing even under the condition of a high current load. In this paper, the effect of some parameters, including the contact diameter (10, 15, and 20 mm), separation speed (0.05–0.3 m/s), and cable inductance in the current commutation path (0.1 and $0.25~\mu \text{H}$) on the threshold current of the arc-less commutation, is investigated by using copper contacts. The results show that a larger contact diameter, slow separation speed, and small commutation cable inductance are good for the improvement of the threshold current of the arc-less commutation. A 200-A current commutation is realized without arc generation, particularly by applying a 20-mm-diameter contact, 0.05-m/s separation speed, and 0.1- $\mu \text{H}$ commutation cable inductance. [ABSTRACT FROM AUTHOR]

The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented. [ABSTRACT FROM AUTHOR]

This paper presents the design, fabrication, and characterization of a module-level spring-interconnected stack power module for power semiconductor devices. The benefit of multilayer design capability offered by a low-temperature cofired ceramic (LTCC) substrate is used for this module-level power module structure. A half-bridge configuration is demonstrated using two standalone wire-bondless power modules with parallel power semiconductor devices stacked on top of each other. An interconnection scheme consisting of conductive copper clamps and a spring-loaded LTCC interposer is adopted to form a module-level 3-D package structure. The low loop and stray parasitic inductances for the 3-D stack are achieved using an antiparallel current path configuration along with the wire-bondless approach and a low-profile spring interposer. For demonstration, silicon insulated-gate bipolar transistors and silicon carbide (SiC) Schottky barrier diodes are used to fabricate the hybrid 3-D stack. Static and transient electrical characteristics of the 3-D stack power module are evaluated through simulation and experimental measurements and compared with a wire-bonded half-bridge power module to investigate the performance improvement in switching characteristics of the 3-D module. High-voltage isolation test, leakage current test, and thermal cycling are performed to validate the spring-interconnected module-level 3-D stack structure. [ABSTRACT FROM AUTHOR]

This paper presents a lumped dynamic electrothermal model of an insulated gate bipolar transistor module of inverters. The thermal model consists of a 3-D network of $RC$ cells constructed for time-dependent operation. The network was found to be precise for determining the temperature excursion of diodes and transistors subsequent to time-dependent power losses. Thermal resistances and capacitances accounting for heat spreading and thermal penetration depth effects were introduced. Electrothermal simulations carried out on a 1200 V–300 A module with a time-dependent average power loss were found to be in good agreement with experiments using infrared thermal imaging. This paper focuses on very-low-frequency behavior (less than 1 Hz) at a switching frequency of 10 kHz. [ABSTRACT FROM AUTHOR]

The reignition of the arc during the interruption process deteriorates the switching performance of low-voltage switching devices (LVSDs). Avoiding reignition is thus a key goal in the effective design of the quenching chamber. A reliable evaluator of reignition provides the opportunity to predict the switching performance of an LVSD during the design process and to refine the product prior to manufacture and empirical device testing. In this paper, reignition evaluators are investigated through the analysis of interruption test data for several types of LVSDs under the single-phase and three-phase circuit conditions. It is observed that the ratio of the recovery voltage to exit arc voltage, where exit arc voltage is defined as the value of the arc voltage immediately prior to the current zero point, is a reliable evaluator for the prediction of reignition in the switching tests of LVSDs. It is also noted that there are no occurrences of instantaneous reignition where this voltage ratio lies in the range from 1 to −1, and there is a threshold of the voltage ratio at approximately −2, which can distinguish the successful interruption and instantaneous reignition. [ABSTRACT FROM AUTHOR]

In order to investigate the long-term behavior of contact resistance in low-voltage contactors under the influence of electric arcs in polymer housings, a new model switch was developed. The model switch permits the modification of different factors such as contact gap, contact force, closing and/or separation speed of the contacts, and arc-chamber materials among others. Several experimental series using Ag/Ni10 contacts were carried out as a reference. The contact resistance was determined using two different measurement current sources. Contact resistance data were analyzed using Weibull functions as well as nonparametric statistics. Information regarding surface structures, their chemical composition, and formed crystalline phases of contact and ambient materials on the contact surfaces was obtained through several material analysis methods. This paper presents the main characteristics of the model switch and some experimental results about contact resistance behavior under the influence of ac-arcs in outgassing polymer surroundings. [ABSTRACT FROM AUTHOR]

This paper presents and discusses results of analysis from investigations of arc-to-glow transformation phenomenon at contact opening, under dc low-energy ( $\leq 10$ J) and low-voltage ( $\leq 250$ V) inductive loads. Dependence of the duration of arcing and glowing on current magnitude, voltage magnitude, properties of the contact material, gas quenching medium velocity and its pressure, as well as contact opening velocity and contact gap are investigated. The transition phenomenon of arc-to-glow is analyzed by means of fast photography and emission spectroscopy. Also discussed is the theoretical evaluation of conditions of arc instability. From the results, possible procedures are formulated to control the arc-to-glow transformation for practical use in dc low-voltage and low-power electrical grids. [ABSTRACT FROM AUTHOR]

In mobile platforms, RF interference issues caused by the switched-mode power supply (SMPS) ringing noise often arise in the on-the-go mode and the charging mode of the interface power management integrated circuits. In this paper, we introduce the modeling method for the SMPS ringing noise in the conventional two-level dc–dc converters and then, based on the modeling insight from the two-level dc–dc converter, we investigate and validate the modeling of the SMPS ringing noise in the three-level buck converters, which are newly adopted SMPSs for fast charging in mobile devices. To reduce such noise, we propose the novel SMPS noise-managing methodologies that handle the printed-circuit-board-level design optimization in mobile devices. [ABSTRACT FROM PUBLISHER]

As more circuit functions are integrated within a single die or small integrated package, the number of electromagnetic interference (EMI) problems caused by dc–dc converters is growing. In this paper, the dominant electromagnetic emission source on the dc–dc converter is identified by analyzing the power spectrum of the nodes. The noise scanner method is applied to a packaged single-chip prototype dc–dc converter. The results show that the dominant source of electromagnetic emission is the switching node of the converter, not the output node. The frequency hopping technique (FHT) is applied to the dc–dc converter to reduce the emission at the switching node, and its effectiveness is analyzed mathematically and experimentally. The mathematical model of FHTs is proposed to analyze its effectiveness in reducing EMI, and the optimal design using the FHT and dead-time control is fabricated with 0.18- \mu \textm CMOS technology. The measured power spectrum reduction by using the optimal FHT design and dead-time control at the switching node is 16 dB. The EMI reduction amount of the proposed design measured by the IC-stripline method is 12.6 dB at the fundamental switching frequency. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a switched-beam four-element antenna array operating at 60 GHz for wireless data transfers between chips in a multichip computing system. The antenna-in-package uses a patterned artificial magnetic conductor to enhance antenna performance. The four-element array has a switchable pattern and shows improved transmission gain compared to previous designs used for data communication between chips. The impact of the array configuration on the switching of the antenna pattern is presented. The wireless link power received between TX and RX nodes is used to evaluate the four-element array antenna design. [ABSTRACT FROM AUTHOR]

In this paper, a study on loss estimation and optimal thermal placement of power electronic modules is presented. The module is a high-voltage inverter with three separated legs, mostly applicable in electric and hybrid vehicles. The loss is estimated using behavioral model and output waveforms obtained from the simulation in MATLAB. This model has used manufacturer’s datasheets in order to facilitate the calculation of heat generation power of both the insulated-gate bipolar transistor and diode. The finite-element (FE) method is used to solve the conductive heat transfer in complex geometry of a three-phase inverter. The heat conduction solution is combined with genetic algorithm (GA) to obtain an effective optimization process of thermal chip placement. In addition, an innovative technique is employed to change the design variables from continuous to discontinuous state and to effectively improve the GA convergence as well as reduce the number of FE simulations. The effectiveness of the proposed method is compared with that of the conventional method, and it shows that both methods resulted in the same optimal placement, whereas FE analysis of the proposed method is about 11.15% of those of conventional methods. [ABSTRACT FROM AUTHOR]

Providing low IR-drop and inductance are two major roles of power and ground (PG) planes in chip packages and boards. However, planes can also cause switching noise coupling, especially when they resonate. This is a concern for mixed-signal boards, high-speed I/Os, and electromagnetic compatibility. Discrete decoupling capacitors are ineffective to control switching noise at gigahertz frequency regime due to their inductance. To filter such high-frequency noise, a possible approach is modifying the shape of the PG planes, such as in power islands or electromagnetic bandgap structures. In this paper, we introduce the nonoverlapping PG planes design methodology for filtering of gigahertz power plane noise. Unlike existing approaches, our approach is simple and has wide bandwidth, while avoiding narrow inductive bridges that increase IR-drop. [ABSTRACT FROM AUTHOR]

In this paper, a novel approach is presented for an integrated analysis of power distribution networks, including dc–dc converters, power transmission lines (PTLs), and multiple loads. The effect of power interconnects is investigated on the dynamic characteristics of a pulsewidth-modulated buck converter. A closed-form relation is developed for control-to-output transfer function including the power interconnects as a transmission line model. The effect of PTLs is demonstrated on converter’s open-loop transfer function and its stability. For analysis of distributed power loads on printed circuit board PTLs, a model is developed based on cascaded matrix representation of interconnects. The model is successfully tested against planar electromagnetic simulation results. [ABSTRACT FROM AUTHOR]

In this paper, the design of RF transceiver front-end using a novel multifunction microwave circuit is proposed. By designing one arm of the proposed active bandpass switchplexer as a bandpass power amplifier (PA) and the other arm as a single-to-balanced bandpass low-noise amplifier (LNA), the resulted multifunctional microwave filtering device thus effectively integrates the functions of single-pole-double-throw RF switch, bandpass filter, balun, PA, and LNA. In this way, all the function blocks between the antenna and up/down converters of a single-band time-division duplex transceiver front-end can be integrated into a single circuit. Compared to the previous works on multifunction microwave circuit designs, the proposed active bandpass switchplexer features the highest number of integrated functions. A printed circuit board-based design example of the proposed active bandpass switchplexer is presented to validate the proposed design concept and to demonstrate the performance achieved. [ABSTRACT FROM PUBLISHER]

Power conversion applications in the low voltage (LV) range (≤ 1.2 kV)—such as three-phase inverters—are required to operate at higher efficiencies, higher ambient temperatures, increasingly smaller form factor, and higher power density. Up to now, most research has focused on voltages up to 650 V for printed circuit board (PCB) embedded power electronics. This research evaluates a novel three-phase invertor module based on six insulated gate bipolar transistors and six diodes rated to 1.2 kV and 25 A each. This unique module is compared to the Semikron MiniSKiiP 23AC126V1. This paper considers some key details of the PCB embedding assembly process, a comparative switching performance assessment, measurement of thermal resistance, comparative lifetime, and electric insulation. First, a detailed outline of the package is presented including the top- and bottom-side metallization and the copper interconnect technology. The switching performances of both modules are compared for turn-ON and turn-OFF currents for a waveform at 600 V and 25 A at 150 °C. A finite-element-method thermal simulation demonstrates up to 44% lower thermal resistance for the PCB embedded package than that of the traditional wire-bonded direct bonded copper (DBC) package for an identical applied current and cooling condition. Furthermore, both packages are active power cycled to failure with the PCB embedded package demonstrating superior lifetime to the traditional DBC module. Finally, the maximum breakdown limit and the onset of partial discharge with the embedded PCB module are reported for both aged and non-aged conditions. The overall findings identify the promising application of PCB embedded power electronics for LV power conversion. [ABSTRACT FROM PUBLISHER]

Recently, a growing number of dc systems exist based on the development of electrical energy consumption. For low-voltage dc grids, switching devices are needed that have to meet technically sophisticated requirements. These devices have to handle fault currents of several hundred amperes and system voltages up to 1000 V. A typical dc circuit breaker has to provide low on-state losses, light weight, and small volume. On the way toward fulfilling these requirements, hybrid circuit breakers can represent the optimal solution. A hybrid dc circuit breaker combines the advantages of mechanical contacts and semiconductors. In this paper, such a device has been designed and constructed using a commercial switch and electronic components in the laboratory. The breaking performance of this experimental prototype has been investigated, and thus the interruption of the nominal and failure currents in the case of different time constants can be identified. The investigated hybrid switching device has been optimized in order to maximize the switching capacity and the protection of the semiconductors. [ABSTRACT FROM PUBLISHER]

Silicon carbide dice are often paralleled to realize power modules with high current rating. Owing to the large network of interconnect (parasitic) impedances, terminal waveforms could appear benign while the dice experience detrimental fault currents generated by spurious cross-turn-on. This paper will quantify the nonuniform distributions of current stress and switching energy among the dice, as well as the penalty caused by cross-turn-on, versus number of dice, gate resistance, input voltage, and switching current. A reliable model for the package is essential. This is demonstrated for a commercial power module with 16 dice, 124 layout inductances, and the companion parallel resistances extracted from the finite-element simulation. Modeling process to avoid convergence problem is developed and verified by the experimental results. For a module tested at 800 V/300 A and carrying six paralleled dice per switch, the cross-turn-on induced current spikes simulated without and with package model differ by as much as 11.75 times. Cross-turn-on increases the high-side switching energy and the total switching energy of the module by 44% and 20%, respectively. One-die, two-die, four-die, and six-die modules are constructed based on the asymmetrical layout to explore how the number of dice influences cross-turn-on and switching energy. Peak cross-turn-on current and total switching energy of the module increase with the number of dice. The peak cross-turn-on current and switching energy of the six-die module are 134% and 36% higher than those of the one-die module, respectively. Severity of cross-turn-on soars as the number of dice increases. [ABSTRACT FROM AUTHOR]

This paper reports the design, fabrication, and characterization of a fully 3-D printed waveguide (WG) and a microfluidically controlled WG switch, operating at K-band. The WG body is printed using a benchtop 3-D printer with thermoplastic substrate acrylonitrile butadiene styrene, and the conductive layer is incorporated using the same printer by automated deposition of conductive silver ink. The measured total insertion loss of the 3-D printed WG is in good match with the simulations showing better than 0.11 dB/cm for the entire K-band. The 3-D printed WG is characterized, and its attenuation and propagation constants are computed for the K-band using a multiline technique. In addition, microfluidically controlled eutectic gallium–indium and galistan liquid metals are integrated with the 3-D printed WG, and a novel reflective WG switch is implemented. The insertion loss and isolation of the switch are measured to be better than 0.5 dB and better than 15 dB for the entire K-band, respectively. Furthermore, the switch’s performance with respect to changes in ambient temperature has been studied. To the best of our knowledge, this is the first time that fused deposition modeling printing and automated ink dispensing is used to fabricate fully 3-D printed WGs, and a 3-D printed WG switch is developed, exhibiting the potential of such technology for rapid prototyping of RF devices. [ABSTRACT FROM PUBLISHER]

3-D integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3-D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2-D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3-D integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting “decap” die and through-vias, are discussed in this paper. [ABSTRACT FROM PUBLISHER]

This paper addresses the generation of accurate and efficient macromodels of high-speed input/output buffers. The proposed modeling approach extends the state-of-the-art methods that are currently available, yielding to a modular and scalable tool for model generation. The modeling procedure applies to both single-ended and differential devices, possibly exhibiting a rich dynamical behavior due to large supply fluctuations or internal voltage regulators. The models are defined by the combination of static surfaces described via compact tensor approximations and linear dynamical state-space relations generated using a robust time-domain vector fitting algorithm. A simple and effective solution is adopted to account for the overclocking operation of output buffer models as well. The feasibility and strength of the proposed method are demonstrated using real devices and complex application test cases for signal and power integrity cosimulations. [ABSTRACT FROM PUBLISHER]

Supply grids of integrated chips are interconnected through through-silicon vias (TSVs) in modern design techniques to form a 3-D stack in vertical direction. The load on each chip is supplied through (power/ground) TSV pairs. Accurate estimation of power/ground noise on each TSV pair of a 3-D power distribution network is necessary for a robust power supply design. The worst case noise obtained with fast switching characteristics may not be significantly accurate. The behavior of power/ground noise as a function of rise time for an inductive power distribution TSV pair with decoupling capacitance, is investigated in this paper. An equivalent rise time corresponding to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. In addition noise sensitivity to decoupling capacitance and TSV inductance is evaluated as a function of rise time. We also discuss noise accumulation as a result of worst case damping factor in this paper. [ABSTRACT FROM PUBLISHER]

This paper discusses the electrothermal characteristics of microelectrical contacts for arcless switching. The 3-D microelectrical contact suitable for dc power-switching application is considered. The important parameters for the design of an arcless microelectrical contact are identified. The ON-state contact resistance and the temperature are calculated and simulated using an Finite Element Method (FEM) tool. In order to design an arcless switching contact, the simulation-based steady-state and transient temperature distributions are estimated. The OFF-state capacitance and the electric field distribution are calculated and simulated for the arcless microelectrical contact. The analysis is carried out for the materials Al, Cu, Au, and Pt. The power ratings of the arcless microelectrical contact are identified. These results can be considered while designing an arcless electrical contact for microswitches, relays, and circuit breakers. [ABSTRACT FROM AUTHOR]

This paper presents a low-phase-noise and wide-tuning-range voltage-controlled oscillator (VCO) implemented in a standard 0.18- \mu \textm complementary metal-oxide–semiconductor (CMOS) process with an integrated passive device (IPD) transformer. Even- and odd-mode oscillations of the transformer-based resonator can be achieved by the mode-switching topology, and the oscillations in the two modes result in a wide tuning range of the VCO. Moreover, the IPD-based transformer achieves high-quality ( $Q$ ) factors ( Q >30$ ), which is impractical in standard CMOS-based technologies due to their lossy silicon substrate. The high- Q$ IPD transformer reduces the phase noise of the VCO and, therefore, leads to a superior figure-of-merit (FOM) and FOM including the tuning range ( ). Operating at 0.8 V supply voltage, the VCO consumes 9.2-mW dc power. At this bias condition, the measured phase noise is −124.2 dBc/Hz at 1-MHz offset from the 6.26-GHz oscillation frequency. Furthermore, the VCO exhibits a 65.7% tuning range and the flipped CMOS chip is packaged on the IPD substrate with a footprint area of 4.35 mm2. Compared with previously published CMOS-based VCOs, the presented VCO features excellent performances in phase noise, wide tuning range, FOM, and \mathrm {FOM}_{T} . [ABSTRACT FROM AUTHOR]

This paper presents a power amplifier module (PAM) that operates efficiently in low-power mode for IEEE 802.11g Wi-Fi applications. The PAM consists of a power amplifier (PA), a buck converter, and a power detector. Two packaging technologies were used to integrate the compact module: a low-temperature co-fired ceramic (LTCC) technology and a ferrite-filled printed circuit board (PCB) technology. The LTCC portion includes radio-frequency inductors, capacitors, transmission lines, and interconnection lines to minimize the overall size, while a power inductor for the buck converter is implemented in ferrite-filled PCB. The PA and the buck converter are designed in 2- \mu \textm InGaP/GaAs heterojunction bipolar transistor technology and 0.35- \mu \textm CMOS technology, respectively. The output power level is converted into a voltage by the power detector, and the voltage controls the buck converter, thereby optimizing the supply voltage of the PA. This adaptive supply voltage helps to improve the power-added efficiency (PAE) in the low-power regime while maintaining linearity. The PAM showed an error vector magnitude of less than 4% up to an output power of 22 dBm. The PAE is 8% and 11% at output powers of 11 and 16 dBm, respectively, representing respective improvements of 60% and 43%. The overall size of the PAM is $5 \times 7.5 \times 1.2$ mm ^{\mathrm {\mathbf {3}}} . [ABSTRACT FROM PUBLISHER]

Laser triggering is interesting for gap switches used in power systems and pulsed power because of its well-controllable delay and jitter time, as well as its electrically uncoupled characteristics. Despite the large attention that was paid to various parameters affect triggering characteristics, the underlying physics of laser triggering remain unclear. In this paper, the nanosecond-laser-triggered pulsed discharge was investigated in atmospheric air. Using a picosecond laser, a high-time-resolution interferometer was constructed and the laser- and discharge-produced plasmas were detected. The shockwaves formed by instantaneous release of the laser and electrical energy into the ambient air were well distinguished. Using the interferograms, phase-shift maps were extracted by a 2-D fast Fourier transform method. Finally, preliminary experiments were performed on laser-triggered discharge from a prototype gap switch, and delay and jitter results were given. [ABSTRACT FROM AUTHOR]

A new gain linearized varactor bank suitable for wideband voltage-controlled oscillators (VCOs) is presented in this paper. The VCO tuning gain linearized techniques, namely the gain variation compensation and linear tuning range extension techniques, are used in the proposed varactor bank to achieve a further reduced VCO tuning gain with low variation. The phase noise from Amplitude Modulation to Phase Modulation up conversion is considerably improved thanks to the reduced VCO tuning gain. Fabricated in a 0.18- \mum CMOS technology, a 3-bits VCO prototype employing the proposed varactor bank achieves <5\% gain variation at the output frequency from 4.1 to 5 GHz, and exhibits maximum power consumption of 7.2 mW at its peak frequency, 5 GHz. [ABSTRACT FROM AUTHOR]

Advances in 3-D integrated circuit (3-DIC) technology have allowed for advantages in integration, system speed, and power consumption for digital systems. In systems operating at very high data rates with large data width, the effect of simultaneous switching noise (SSN) can, however, drastically affect system performance. Therefore, the effect of SSN in the power delivery network (PDN) design of a through silicon via (TSV)-based 3-D stack has been investigated in this paper, and eye diagrams have been simulated in each level of the stack to analyze power supply noise and transition jitter. Using a novel PDN design concept based on constant voltage power transmission lines, it is shown that this new PDN design can significantly improve signal quality in a 3-DIC application. The 3-D system considered here consists of a PCB, an interposer, and three IC dies. Each IC contains a TSV layer, PDN, and digital logic. [ABSTRACT FROM PUBLISHER]

In this paper, a new method is proposed to model the simultaneous switching noise (SSN) using time-domain impedance function, which is based on the rational function in time domain. The time-domain impedance function of a power delivery network (PDN) is calculated by approximating the impedance frequency response of a PDN with a rational function, and the SSN is calculated based on switching current characteristics, which is verified by advanced design system, Hspice and measurements. Based on time-domain impedance function, the SSN suppression is also investigated, and it is found that the SSN produced by periodic switching current can be suppressed through adjusting the periods of time-domain impedance function and switching current, and a principle for random switching current is also given to prevent the occurrence of the worst case of SSN in circuit design. [ABSTRACT FROM AUTHOR]

High voltage switches capable of operating at high speeds with high current levels are used in a variety of applications in commercial and government systems. This paper discusses the fabrication and characterization of a novel micromachined planar triggered spark gap switch. The switch provides a low cost alternative to conventional triggered spark gap switches. The structure is designed for direct integration into the strip-line geometries used in a conventional capacitive discharge unit. The geometry of the device was selected to minimize parasitic impedances associated with conventional firing circuits. [ABSTRACT FROM PUBLISHER]