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Excessive switching activity in the fault-free circuit can cause a fault-free circuit to fail because of increased delays. For the same reason, excessive switching activity in a faulty circuit can cause a delay fault to escape detection. This paper observes that the switching activity is higher in the presence of multiple delay faults with higher multiplicities (larger numbers of single faults that are present in the circuit together). The challenge in addressing multiple faults is related to their large number. This paper addresses this challenge by an iterative procedure that is applied to transition faults under a low-power broadside test set, and has two subprocedures: 1) the first subprocedure finds multiple transition faults with excessive faulty switching activity and 2) the second subprocedure modifies the test set so as to avoid excessive faulty switching activity for the faults found by the first subprocedure. With every additional iteration there are fewer multiple transition faults that exhibit excessive faulty switching activity. The experimental results for benchmark circuits demonstrate the levels of excessive faulty switching activity in the presence of multiple transition faults, and the possibility of reducing or even eliminating it after a small number of iterations. [ABSTRACT FROM AUTHOR]

This paper defines a new type of a low-power broadside test, called a reverse low-power broadside test, whose application requires design-for-testability logic. The unique feature of a reverse low-power broadside test is that it duplicates the switching activity during the second functional capture cycle of a given low-power broadside test, except that signal-transitions are reversed. Thus, the switching activity of a reverse low-power broadside test duplicates that of a low-power broadside test in every subcircuit and on every line individually. In addition, the reversed test detects different faults, and can thus increase the fault coverage of a low-power broadside test set. This paper studies the ability of reverse low-power broadside tests to increase the transition fault coverage in benchmark circuits considering functional broadside tests as well as low-power broadside tests that are not functional. [ABSTRACT FROM AUTHOR]

Scan-based tests that maintain close-to-functional operation conditions are important for avoiding overtesting of delay faults while achieving the fault coverage required for avoiding test escapes. For a measurable proximity to functional operation conditions, partially functional broadside tests have a known Hamming distance between their scan-in states and reachable states. Another parameter that is important for the discussion of overtesting is the switching activity. This paper suggests a combined metric, where a reduced switching activity is taken as a safety margin that allows a higher Hamming distance between the scan-in state and a reachable state. The metric is defined such that a value of 100% or lower is preferred. To demonstrate that the metric is flexible enough to allow tests to be generated, the paper describes a test generation procedure that uses the metric. [ABSTRACT FROM PUBLISHER]

Bayesian inference is an effective approach for solving statistical learning problems, especially with uncertainty and incompleteness. However, Bayesian inference is a computing-intensive task whose efficiency is physically limited by the bottlenecks of conventional computing platforms. In this paper, a spintronics-based stochastic computing (SC) approach is proposed for efficient Bayesian inference. The inherent stochastic switching behaviors of spintronic devices are exploited to build a stochastic bitstream generator (SBG) for SC with hybrid CMOS/magnetic tunnel junction (MTJ) circuits design. Aiming to improve the inference efficiency, an SBG sharing strategy is leveraged to reduce the required SBG array scale by integrating a switch network between SBG array and SC logic. A device-to-architecture level framework is proposed to evaluate the performance of spintronics-based Bayesian inference system (SPINBIS). Experimental results on data fusion applications have shown that SPINBIS could improve the energy efficiency about $12 {\times }$ than MTJ-based approach with 45% design area overhead and about $26 {\times }$ than FPGA-based approach. [ABSTRACT FROM AUTHOR]

Phased array element RF front ends typically use single pole double throw switches or circulators with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased-array designs scale to the millimeter-wave range, with high degrees of integration, physical size, and performance degradations associated with switches and circulators can present challenges in meeting system performance and SWAP requirements. This paper provides a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits. The methodology provides design insights and a practical, generally applicable approach for solving the multivariable optimization problem of switchless power amplifier/low-noise amplifier (PALNA) matching networks, which present optimal matching impedances to both the PALNA while maximizing power transfer efficiency and minimizing dissipative losses in each T/R mode of operation. An example design in global foundries 32SOI CMOS at W-band using the proposed methodology is presented. The design achieves simulated maximum power added efficiency of 18% in transmit and noise figure of 7.5 dB in receive at 94 GHz. [ABSTRACT FROM AUTHOR]

Test vector omission allows the length of a functional test sequence to be reduced without reducing its fault coverage. When a circuit is embedded in a design, the omission of test vectors from a functional test sequence for the circuit may result in a sequence that does not satisfy the functional constraints imposed by the design. This paper addresses this issue by developing a procedure that restores omitted test vectors in order to satisfy functional constraints. For the discussion in this paper, functional constraints are captured by the switching activity of the sequence before any test vectors are omitted from it. This is referred to as its functional switching activity profile. Experimental results demonstrate that the length of a sequence can be reduced even after restoration of omitted test vectors based on its functional switching activity profile. [ABSTRACT FROM AUTHOR]

Advances in semiconductor technology enable integrating tens of cores on a single chip. Providing quality-of-service (QoS) for communication flows in complex embedded applications is critical. In this paper, we present a new approach for designing guaranteed service (GS) networks-on-chip by introducing a new arbitration algorithm and differentiating high and low priority traffic flows in best-effort (BE) networks. An analytical model is provided to compute accurate performance bound parameters in the network with the new arbitration. When the flows have the same priorities in a switch, the new algorithm acts exactly the same as the basic round robin arbitration. It works as a superset of the basic algorithm, when the flows have different priorities. The proposed method helps designers to easily equip traditional BE networks with effective hard QoS, changing it to a GS network. This is done without the need to get involved in the designing complexity of traditional GS networks and still benefit from the superior properties of BE networks. We show substantial improvement in performance bounds for high priority flows (more than 40% in delay and 80% in bandwidth, on average) compared to the known approaches. [ABSTRACT FROM PUBLISHER]

Magnetic tunnel junction (MTJ)-based devices have been studied extensively as a promising candidate to implement hybrid energy-efficient computing circuits due to their nonvolatility, high integration density, and CMOS compatibility. In this paper, MTJs are leveraged to develop a novel full adder (FA) based on 3- and 5-input majority gates. Spin Hall effect (SHE) is utilized for changing the MTJ states resulting in low-energy switching behavior. SHE-MTJ devices are modeled in Verilog-A using precise physical equations. SPICE circuit simulator is used to validate the functionality of 1-bit SHE-based FA. The simulation results show 76% and 32% improvement over previous voltage-mode MTJ-based FA in terms of energy consumption and device count, respectively. The concatanatability of our proposed 1-bit SHE-FA is investigated through developing a 4-bit SHE-FA. Finally, delay and power consumption of an n -bit SHE-based adder has been formulated to provide a basis for developing an energy efficient SHE-based n -bit arithmetic logic unit. [ABSTRACT FROM PUBLISHER]

Resistive switching devices are nonlinear electrical components that have drawn great attention in the design of new technologies including memory devices and neuromorphic circuits. In this paper, an SPICE implementation of a novel compact model is presented and put under test by means of different circuit configurations. The model is based on two identical opposite-biased diodes in series with a resistor where the switching behavior is governed by the creation and rupture of multiple conductive channels. Results show that the model is stable under different input sources and amplitudes and, with special interest, in multielement circuits. The model is validated with experimental data available in the literature. Both the corresponding SPICE code and schematic are provided in order to facilitate the model use and assessment. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology due to its various advantageous features such as scalability, nonvolatility, density, endurance, and fast speed. However, the reliability of STT-MRAM is severely impacted by environmental disturbances because radiation strike on the access transistor could introduce potential write and read failures for 1T1MTJ cells. In this paper, a comprehensive approach is proposed to evaluate the radiation-induced soft errors spanning from device modeling to circuit level analysis. The simulation based on 3-D metal-oxide-semiconductor transistor modeling is first performed to capture the radiation-induced transient current pulse. Then a compact switching model of magnetic tunneling junction (MTJ) is developed to analyze the various mechanisms of STT-MRAM write failures. The probability of failure of 1T1MTJ is characterized and built as look-up-tables. This approach enables designers to consider the effect of different factors such as radiation strength, write current magnitude and duration time on soft error rate of STT-MRAM memory arrays. Meanwhile, comprehensive write and sense circuits are evaluated for bit error rate analysis under random radiation effects and transistors process variation, which is critical for performance optimization of practical STT-MRAM read and sense circuits. [ABSTRACT FROM PUBLISHER]

Fan proposed a set of hyperuniversal switch blocks (HUSBs), called Fan’s (4, w )-HUSBs in this paper. He also proved that his design with w less than 6 was optimum. That is, they used the least switches to achieve hyperuniversal routability. However, we find a counter example to show that there is an unnecessary switch in Fan’s (4, 4)-HUSB. Namely, we propose a new (4, 4)-HUSB, water-molecule-shaped switch block (WMSB), proving (4, 4)-WMSB with 24 switches is optimal. Furthermore, we also propose optimal (4, 7)-WMSB, which is a (4, 7)-HUSB with 42 switches. [ABSTRACT FROM PUBLISHER]

As advances in manufacture technology, leakage current increases dramatically in modern ICs. By turning off supply voltage in a low-power domain with power switches, power gating becomes a useful technique in resolving this problem. Since number and locations of power switches have great impact on chip area and IR-drop, an efficient and effective approach to insert power switches is required for the power gating designs. Unlike previous works using the greedy algorithm to handle this problem, this paper uses a simplified model to approximate required equivalent resistance of power switches in a low-power domain, and then determines number and types of power switches based on the value. In order to reduce impact on preplaced standard cells, we also propose a mathematical approach to find locations with less placement density to place power switches. The proposed methodology was integrated into a real-design flow. Experimental results demonstrate that our approach can insert less number of power switches and still satisfy the IR-drop constraint than other approaches. [ABSTRACT FROM PUBLISHER]

The development of emerging spin-transfer torque random access memory (STT-RAM) is facing two major technical challenges—poor write reliability and high write energy, both of which are severely impacted by process variations and thermal fluctuations. The evaluations on STT-RAM design metrics and robustness often require a hybrid simulation flow, i.e., modeling the CMOS and magnetic devices with SPICE and macro-magnetic models, respectively. Very often, such a hybrid simulation flow involves expensive Monte Carlo simulations when the design and behavioral variabilities of STT-RAM are taken into account. In this paper, we propose a fast and scalable semi-analytical method—PS3-RAM, enabling efficient statistical simulations in STT-RAM designs. By eliminating the costly macro-magnetic and SPICE simulations, PS3-RAM achieves more than 100 \(000\boldsymbol {\times }\) runtime speedup with excellent agreement with the result of conventional simulation method. PS3-RAM can also accurately estimate the STT-RAM write error rate and write energy distributions at both magnetic tunneling junction switching directions under different temperatures, demonstrating great potential in the analysis of STT-RAM reliability and write energy at the early design stage of memory or micro-architecture. [ABSTRACT FROM AUTHOR]

Functional broadside tests are useful for guiding a low-power test generation procedure by providing a target for the switching activity of low-power tests. Low-power test generation procedures based on functional broadside tests first generate a set of functional broadside tests. They then use the tests for guiding the generation of low-power non-functional broadside tests that are required for increasing the fault coverage. In the low-power test generation procedure described in this paper, functional and non-functional broadside tests are generated simultaneously by the same process. In addition to the simplicity that this provides, it also requires fewer functional broadside tests that detect target faults to be generated. Moreover, it allows stricter constraints on the switching activity of non-functional broadside tests to be satisfied. These constraints prevent a non-functional broadside test from compensating for an excessively high switching activity in one sub-circuit with a low switching activity in another. [ABSTRACT FROM PUBLISHER]

In phylogenetic inference, which aims at finding a phylogenetic tree that best explains the evolutionary relationship among a given set of species, statistical estimation approaches such as maximum likelihood (ML) and Bayesian inference provide more accurate estimates than other nonstatistical approaches. However, the improved quality comes at a higher computational cost, as these approaches, even though heuristic driven, involve optimization over multidimensional real continuous space. The number of possible search trees in ML is at least exponential, thereby making runtimes on even modest-sized datasets to clock up to several million CPU hours. Evaluation of these trees, involving node-level likelihood vector computation and branch-length optimization, can be partitioned into tasks (or kernels), providing the application with the potential to benefit from hardware acceleration. The range of hardware acceleration architectures tried so far offer limited degree of fine-grain parallelism. Network-on-chip (NoC) is an emerging paradigm that can efficiently support integration of massive number of cores on a chip. In this paper, we explore the design and performance evaluation of 2-D and 3-D NoC architectures for RAxML, which is one of the most widely used ML software suites. Specifically, we implement the computation kernels of the top three functions consuming more than 85% of the total software runtime. Simulations show that through appropriate choice of NoC architecture, and novel core design, allocation and placement strategies, our NoC-based implementation can achieve individual function-level speedups of 390x to 847x, speed up the targeted kernels in excess of 6500x, and provide end-to-end runtime reductions up to 5x over state-of-the-art multithreaded software. [ABSTRACT FROM PUBLISHER]

Power supply noise (PSN) has become a critical issue during high-quality at-speed testing. Discrepancies between the circuit's switching activity during functional and test mode can cause overtesting and lead to yield loss. Alternatively, reduced PSN effects around critical paths can result in undertesting the chip, causing test escapes. To achieve a high-quality at-speed test, it is necessary to solve these problems simultaneously. Our previous work introduced a noise index model (NIM), which can be used to predict the mismatch between expected and real path delays. This paper quantitatively investigates and compares NIM values for critical paths during functional and test mode. We then propose a test pattern modification method that harnesses the NIM. The method fills a subset of the don't care bits in partially specified test vectors such that the worst observed functional NIM for the targeted critical path is replicated during test mode. [ABSTRACT FROM PUBLISHER]

Due to the increasing chip temperature and the strong dependency of leakage power on temperature, thermal aware power management has received a considerable amount of attention recently in energy efficient system design. In this paper, we propose a temperature-aware intra-task scheduling algorithm to minimize leakage energy in real-time systems. The basic idea of our algorithm is to run tasks at full speed when the chip temperature is low or the work urgency is high, and switch the processor to a low-power state when the chip temperature is high or the workload is light. Our offline algorithm can achieve the optimal leakage reduction for a given task with the worst-case execution time, while the online algorithm has a very low runtime complexity. The simulation results show that the online algorithm is able to reduce 34% of total leakage energy on average in both real-world and artificial benchmarks. Finally, we demonstrate how to combine our algorithm with existing dynamic voltage scaling technique to optimize the overall energy consumption. [ABSTRACT FROM AUTHOR]

The power dissipation during the application of scan-based tests can be significantly higher than during functional operation. An exception is the second, fast functional capture cycles of functional broadside tests, where it is guaranteed that the power dissipation will not exceed that possible during functional operation. The power dissipation during the other clock cycles of functional broadside tests is studied here for the first time. The clock cycles under consideration are referred to as scan shift cycles. This paper describes a test generation procedure that limits the power dissipation during scan shift cycles of functional broadside tests. Experimental results for benchmark circuits demonstrate the extent to which the power dissipation during scan shift cycles can be limited without affecting the transition fault coverage. [ABSTRACT FROM PUBLISHER]