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The field-plate (FP) technique suppresses the electric field crowding at the p-n junction by inducing the interface charges in the drift region. However, due to the modeling difficulty, the physical meaning cannot be elaborated via the conventional 2-D methods, not to mention the designing optimization. Therefore, the FP assistant reduced surface field effective concentration profile (ECP) is proposed in this paper to explore the physical insight of the FP assistant 2-D coupling. The ECP simplifies the sophisticated 2-D coupling by equating the FP assistant effect to the variation of the ECP. As a result, a simple and effective 1-D analytical model is presented to qualitatively and quantitatively explore the FP-induced surface field reshaping and its distinctive breakdown mechanism. The analytical solutions are found out to be consistent with the simulation results obtained from MEDICI, a commercial TCAD tool. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

In this paper, subthreshold channel potential, current, swing, threshold voltage, and drain-induced barrier lowering models of short-channel tri-gate junctionless field-effect transistors are presented. The models incorporate the effects of both substrate-induced surface potential and variable edges of channel. The quasi-3-D approach is used for the modeling of minimum of channel potential that is subsequently used in the drift–diffusion equation to obtain the current expression in subthreshold regime. Threshold voltage and subthreshold swing models are also based on the minimum of channel potential. The analytical results are compared with the simulation data obtained using 3-D visual TCAD device simulator from Cogenda Pvt., Ltd. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator. [ABSTRACT FROM AUTHOR]

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX. [ABSTRACT FROM AUTHOR]

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton–Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface. [ABSTRACT FROM PUBLISHER]