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Conventional half bridge modular multilevel converter (MMC) system will suffer great over-current when there is a dc side fault. Therefore, topology study in sub-modules with dc side fault blocking capability have become one of the hotspots in MMC field. However, fault blocking topologies using conventional IGBT devices must employ more semiconductors than half bridge topology. The extra semiconductor devices employed in the topology will lead to the increase of cost and conduction loss. To reduce the conduction loss of the fault blocking topology, a novel sub-module topology is proposed in this paper. The proposed topology employs reverse blocking devices to form the low conduction loss path. Conduction loss analysis is conducted in this paper to show the priority of the proposed topology. Simulation and experiment results verified the dc fault blocking capability of the proposed topology. [ABSTRACT FROM AUTHOR]

Protection of microgrids at the Point of Interconnection (POI) is a challenging task. Particularly, single-line-to-ground (SLG) faults on interconnection lines are difficult to detect using the fault current detection relays if the microgrid is ungrounded at utility side of its interconnection transformer; such microgrid contributes very low fault current, which disappears once the utility feeder breaker opens. Other common schemes for protection of microgrid interconnection line against SLG faults include Direct Transfer Trip (DTT) and over-voltage relay (59G). The main challenges associated with these methods are installation and maintenance costs of high-speed communication system, sensitivity of relay settings, and delayed fault clearing time due to selectivity requirements. To address such concerns, this paper proposes the use of a distance relay at the microgrid/LV side of the interconnection transformer to provide protection against SLG faults on the interconnection line at the utility/HV side. The designed distance relay executes an enhanced apparent impedance calculation using residual voltage compensation to correctly detect the fault, properly measure the fault location, and timely isolate the fault. In this paper, various scenarios are analyzed using ASPEN and PSCAD simulation tools to demonstrate the effectiveness of the proposed method for protecting the microgrid interconnection line under different fault scenarios. [ABSTRACT FROM AUTHOR]

The short-circuit response of inverter-interfaced distributed generators (IIDGs) is not adequately represented in many conventional protection studies. This paper presents an in-depth analysis of IIDG behavior during grid faults and proposes a more accurate reduced-order parameterized short-circuit current (RPSC) model of inverters. Typical inverter components are thoroughly investigated to identify those that play dominant roles during faults. The paper shows that the current limiter is the dominant factor for the steady-state fault-current of inverter; while the inverter filter along with the severity of the voltage disturbance largely determine the initial transient spike of inverter fault current. The proposed model is low-order and can be used in large scale simulations. The parameters of the proposed RPSC model can be extracted from laboratory experiments without requiring proprietary manufacturer information. The proposed fault-current model is analogous to the well-known synchronous machine model that segregates the inverter fault current into subtransient, transient, and steady-state fault currents. Experimental and simulation tests are presented to validate the model. [ABSTRACT FROM AUTHOR]

This paper presents the DC fault transient study of a meshed DC grid with high-temperature superconducting (HTS) HVDC cables to integrate offshore wind power. A four-terminal meshed DC grid model with a ±100 kV DC voltage rating is developed. DC circuit breakers (DCCBs) are implemented in the DC grid to deal with DC cable faults. To conduct the fault transient study, the fault scenarios with different fault locations and protection delays are studied. The sensitivity study versus different DC fault locations reveals that the faults on the faulted cable will not cause the quenching of healthy cables. The sensitivity study considering different DC fault protection delays demonstrates that the HTS cables have a current-limiting effect and the long delay of DC fault protection does not result in large fault current and the quenching of healthy cables. Extensive simulations in PSCAD/EMTDC validate the founding. [ABSTRACT FROM AUTHOR]

The single-phase to ground fault (SPGF) is very common in power grids. To decrease the fault’s influence on the power supply’s reliability, the neutral point is usually grounded via the Petersen coil, significantly reducing the outage rate. Nevertheless, this coil would weaken the fault current and make the faulty line identification much more difficult. To address such an issue, an identifying method for the faulty line is proposed in this paper based on the detection of an extremely low frequency current(ELFC), after analyses are made on the electrical signal’s characteristics when the fault exists based on a common physical model of a medium-voltage distribution system. Then, to coordinate with this method, a set of devices are developed to accurately measure the ELFC and ensure feasibility. At last, a simulation and an experiment are conducted, and the results prove this method’s validity in the identification of a faulty line. [ABSTRACT FROM AUTHOR]

Flexible DC distribution networks have been widely developed because of their advantages of high efficiency, low cost, and easy access to renewable energy. However, as distribution networks have more ends than the two-terminal transmission line, it is more challenging to protect them and locate their faults. Therefore, this paper proposes a modified T-source circuit breaker to protect against DC faults. Based on the proposed circuit breaker, an integral fault location method using double-terminal asynchronous data is proposed. The accuracy of the algorithm is not affected by the fault resistance. There are no differential terms in the algorithm, which greatly reduces the sensitivity to noise. The integral algorithm can remain steady when the voltage and current are zero in oscillation and attenuation periods. This constitutes the main contribution of this paper. Finally, it is verified by simulation and experiment that the proposed circuit breaker can isolate the power source within a short time in the typical DC distribution network. Under a noise of 30 dB for simulation, the location error of the proposed algorithm is <0.4% when the fault resistance is 0.5 Ω–500 Ω. [ABSTRACT FROM AUTHOR]

The penetration of inverter-based resources is growing rapidly around the globe. During a fault, the behavior of inverter-based resource is very different from a traditional synchronous machine based generation. As the penetration of inverter-based resources increases, there is an urgency for the industry to understand their behavior so that these resources can be accurately modeled and their impact on various protection schemes can be studied in detail. This path begins with standardizing the response of inverter-based resources to a fault. Additionally, this paper discusses issues with modeling inverter-based resources in a short circuit model which is developed for systems dominated by synchronous machines and finally a need for further research to understand impacts on traditional protection schemes as inverter-based resources continue to displace traditional generation. This paper does not offer solutions however, it is intended to encourage further study by industry professionals toward development of solutions. [ABSTRACT FROM AUTHOR]

When a fault occurs on the dc side of the voltage source converter based high voltage direct current (VSC-HVDC) transmission system, the fault current rises quickly due to the low damping of the dc system. Using a dc fault current limiter (DC-FCL) to limit the rise of the fault current can significantly reduce the breaking requirements of the DCCB. A topology of a bidirectional active dc fault current limiter (BA-FCL) based on coupled inductor is proposed in this paper. No expensive full-controlled power electronic devices are used in this topology. Only a few half-controlled power electronic devices are used to achieve active control of the current limiting unit. Compared with many topologies of current limiter at present, the fault current limiting effect of BA-FCL is improved significantly while the cost, volume, topology complexity, and control complexity are reduced. The stress analysis and parameter design of the proposed current limiter are carried out. Finally, the simulation case study and hardware experiment are implemented to verify the good economy and current limiting performance of the proposed topology. [ABSTRACT FROM AUTHOR]

Due to the complex structures and fault conditions, accurate fault sensing of the underground distribution cables is a difficult task. The distribution automation system (DAS) and fault indicator system (FIS) are only applicable to the severe faults. In addition, the current DAS and FIS are all based on the centralized data processing system (CDS), increasing the communication pressure and data processing time of the main station. Considering the advantages of edge computing, this paper investigates using the grounding line currents to sense the fault in distribution cable networks. First, an edge computing based fault sensing system (ECS) is designed. The equivalent time-domain distribution cable models considering multi-conductor mutual couplings are then established in both normal and fault cases. The time-domain features of the cable grounding line currents prior to and after the fault are analyzed to create the fault detection criterion. Combining the network topology, locations of the measurement units (MUs), and direction factor of the ground line current, a space matrix based algorithm is created to achieve fault cable section location at edge. Finally, a distribution cable network is created by PSCAD/EMTDC. Various simulations are conducted to validate the effectiveness and robustness of the algorithm. [ABSTRACT FROM AUTHOR]

Piezoelectrically actuated fast mechanical switches provide a low-loss conduction path in hybrid circuit breakers for protecting medium-voltage direct-current systems. As the desired actuation speed approaches the driving limit of a piezoelectric actuator, excessive vibration starts to dominate its underdamped travel curves, resulting in insulation failures and delayed switching in the fast mechanical switch. To improve the underdamped travel curves into critically damped travel curves, several switching motion control schemes with active damping filters are proposed in this paper. The switching motion controllers are based on an electromechanical model of a fast mechanical switch with experimentally identified parameters. According to hardware implementation tests, the proposed closed-loop control schemes optimized the switch travel curves with a 56% reduction in the undershoot and a 75% reduction in the settling time. Equipped with the critically damped travel curves, the piezoelectrically actuated fast mechanical switch is better suited for sequential submodule operations to reduce the interruption time, the peak current and the fault energy to be absorbed in hybrid circuit breakers. [ABSTRACT FROM AUTHOR]

The classical electromagnetic time reversal (EMTR) fault location method in power systems requires multiple simula-tions in the backward step, assuming different guessed fault loca-tions along the line. This process can be time consuming especially when a high location accuracy is desired, as it may require a significant number of guessed fault locations. To cope with this issue, the concept of EMTR in mismatched media has recently been introduced, allowing reducing the backward simulations to a single run and, thus, substantially improving the computation efficiency of the EMTR-based fault location technique. In this paper, we present a detailed study of the mismatched-media-based mirrored minimum energy property. This property has been applied in a few recent studies but never been theoretically studied and rigorously demonstrated. First, we infer a transfer function that relates the fault source to the voltage along the line resulting from back-injecting the time-reversed transients measured at a given observation point. We present a theorem according to which, at the fault switching frequency and its odd harmonics, the mirror-image point of the fault location with respect to the line center corresponds to a local minimum of the squared modulus of the transfer function. Then, it is proved that the mirrored minimum energy property is a corollary of this theorem. Based on these theoretical findings, we propose an algorithm that utilizes the reversed-time voltage energy as a fault location metric in the frequency domain. We further advance a data-driven strategy to maximize the computation efficiency of the fault location procedure. The applicability and robustness of the proposed frequency-domain fault location metric are numerically and experimentally validated. [ABSTRACT FROM AUTHOR]

The full-cycle discrete Fourier transform (FCDFT) is commonly used to estimate phasors in numerical relays because of its immunity to harmonics and accurate identification of a decaying dc component (DDC) in a fault current. For fast protection of power systems, it is necessary to speed up the phasor estimation by using a data window below one cycle. The conventional least squares (LS) methods below one cycle approximate the DDC as the first several terms of the Taylor series expansion, which degrades the phasor-estimation accuracy. This paper proposes an LS method that uses Fourier analysis for approximation of the DDC to speed up phasor estimation without accuracy degradation. The phasor-estimation accuracy of the proposed method is investigated for the data-window length in simulations using synthetic data of fault currents containing DDC, harmonics, and measurement noise. The phasor-estimation speed is also investigated with respect to the delay of the antialiasing filter in the numerical relay. The proposed method is compared with the conventional LS and FCDFT methods in simulations using synthetic fault-current data. The feasibility of the proposed method is demonstrated through the phasor estimation of simulated transmission-line faults. [ABSTRACT FROM AUTHOR]

The vacuum interrupter-based DC circuit breaker is one of the most important equipments in the DC power system. The dielectric recovery (DR) of vacuum interrupter (VI) is essential for breaking reliability, especially on some occasions with ultra-large fault current such as the outlet of generator. To measure the DR of VI under high arcing current, an experiment circuit is designed and the DR under arcing current from 20 kA to 60 kA is presented in this paper. The influence of arcing current, contact separation, di/dt before current zero and arcing time on the DR is investigated. Particularly, it's found that under a specific arcing current, there exists an optimal arcing time for DR, and it shows a negative correlation with the arcing current. [ABSTRACT FROM AUTHOR]

Most microgrid protection schemes found in published literature suffer from a lack of generality in that they work well for the assumed topology, including type and placement of sources. Other generic protection schemes tend to be too complicated, too expensive, or both. To overcome these drawbacks, a topology-agnostic, scalable, and cost-aware protection based on fundamental principles that work in the presence of high penetration of inverter-based resources (IBRs) is developed and tested in this paper. The protection system also implements stable automatic reconfiguration of the healthy sections of the system after clearance of fault, thus increasing resilience by self-healing. To achieve this ambitious goal, stable inverter models are developed that operate in unbalanced networks in grid-connected and islanded modes, even with 100% IBRs, share power without conflicting controls, and can ride through faults while limiting fault currents. The scheme is tested for primary and backup protection and reconfiguration on the IEEE 123-node feeder in grid-connected and islanded modes with 15 IBRs connected to the system. [ABSTRACT FROM AUTHOR]

The single-phase-to-ground (SPG) fault at the valve side of the converter transformer is one of the most critical faults threatening the operation of bipolar half-bridge modular-multilevel-converter-based multi-terminal direct-current (HB-MMC MTDC) systems. Following a valve-side SPG fault, the upper-arm submodule (SM) capacitors in the faulty converter may suffer a serious overvoltage, and the grid-side fault currents may experience no zero-crossings. The existing protection methods generally rely on tripping the grid-side alternate-current circuit-breaker (ACCB), which cannot fully isolate the fault. The healthy poles and stations may encounter severe disturbance and be all blocked, which will lead to a power outage of the entire MTDC system. This paper proposes an ACCB-independent scheme based on thyristor-pairs and damping SMs to address these problems. Antiparallel thyristor-pairs are connected in series within the upper and lower arms in each phase. Serial damping SMs are connected within the lower arms to help the lower-arm thyristor pairs cut off the fault currents. Although the proposed additional devices inevitably cause conduction losses, they can effectively protect the faulty converter and healthy circuit in the MTDC system. Simulations in PSCAD/EMTDC have been conducted to verify the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

Most of the available directional relaying schemes use the phase angle information of sequence components of voltage and current with a cycle or more as the decision time. Converter interfaced solar photovoltaic plants are subjected to follow grid codes, leading to significant voltage and current modulation compared to conventional synchronous machines based sources. This may result in malfunction of existing directional relaying. This paper presents a high-speed time-domain directional relaying method using only phase fault current for distribution systems in the presence of solar plant. The method proposes a fault direction discrimination function, and its sign provides the direction of fault. The proposed method is tested for various control options embedded in solar plant, fault parameters, and noisy signals in CIGRE 14-bus distribution system integrating solar plant. Results validate the ability of the proposed method to decide within one-fourth of a cycle following fault detection for both PV plant side as well as grid end. Comparative assessment reveals the superiority of the proposed current based direction relaying method over the existing technique. [ABSTRACT FROM AUTHOR]

The current-limiting inductors (CLIs) are commonly used to suppress DC fault current to safely trip DC circuit breakers in MMC-HVDC systems, but it significantly jeopardizes DC dynamics and causes instantaneous power mismatch between AC and DC sides of islanded rectifier station (RS), exposing MMC internal states to large disturbance. This paper firstly provides a detailed analysis of the influence of CLIs on AC fault, establishes RS mathematical representation including AC side dynamic, and reveals the mechanism of DC voltage oscillation, modulation saturation and PCC waveform distortion. The analysis shows that the AC and DC fault characteristics are decoupled under unsaturated AC modulation, but coupled under excessively low submodule capacitor voltage, where AC modulation is saturated and PCC waveforms are distorted. To solve this issue, a novel RS AC fault ride through method for MMC-HVDC system with CLIs is proposed to stabilize RS DC voltage, desaturate AC modulation and decouple fault characteristics by regulating the zero-sequence modulation of circulating current suppression. In addition, a current reference disturbance and an AC energy dissipation device coordinated control are designed, which adaptively recovers the submodule capacitor voltage. Finally, the feasibility of the proposed method is verified by simulation results. [ABSTRACT FROM AUTHOR]

The HVDC systems have been employing modular multilevel converters (MMC) due to their unique high voltage high power potential. However, the lack of fault ride-through capability imposes restrictions on MMCs that are based on half-bridge (HB) modules. Since it is necessary to limit the fault currents to protect MMCs from serious short circuit faults against pole-to-pole DC fault, several protection schemes have been introduced to deal with the DC short circuit faults. This paper proposes a new hybrid MMC protective topology consisting of a combination of the HB and three-quarter-bridge (TQB) modules. The TQB behaves like an HB under normal operation and has low power losses compared to other protective topologies. Modulation and control of this configuration are like HB-based MMC. In the proposed hybrid protective topology, during a pole to pole DC fault, the fault current can be either blocked or be limited by TQB-SMs. Both simulations and experiments were performed to verify the operation of the suggested hybrid MMC in different modes of operation. [ABSTRACT FROM AUTHOR]

Cables short circuit withstand-capacity plays a crucial role in medium voltage distribution system design. For a given short circuit level at substation, fault current at any point in a radial distribution system depends on the location with respect to the substation, distributed generation as well as size and length of upstream cable sections. This paper addresses optimal routing, cable sizing, distributed generation allocation and sizing of radial medium voltage power distribution network considering cables short circuit withstand capacity. Both synchronous-based and inverter-based distributed generators are considered. Complete formulation of cables short circuit constraints (SCCs) is introduced in mixed-integer linear programming (MILP) form. A Benders-decomposition-based approach is used to solve the problem by considering short circuit at each system bus in a separate slave feasibility problem. Combinatorial cuts are proposed to exclude infeasible solutions in each iteration by investigating upstream routes, cable sizes and distributed generation. The proposed optimization framework and solution algorithm are applied on 54 bus, 84 bus and 138 bus systems. The results revealed potential saving in investment, maintenance and losses costs compared to upgrading method. Also the proposed solution algorithm showed great saving in the number of added constraints to the original problem. [ABSTRACT FROM AUTHOR]

The high di/dt before zero-crossings easily leads to delayed or failed operations for the active current injection mechanical DC circuit breaker, especially for small direct current interruptions. The pre-charging process also makes this type of circuit breaker hard to realize repeat operations economically in the high voltage DC system. This paper proposes a novel DC circuit breaker and its design method that deeply coordinating a superconducting fault current limiter with the active current injection DC circuit breaker. This method significantly reduces di/dt before current zero-crossings and enables repeat operations economically. Besides limiting fault currents, the superconducting fault current limiter also charges the resonance capacitor flexibly in the circuit breaker, realizing the injected reverse current keep a constant proportion to the arbitrary fault current. Validations of the flexible capacitor charge and repeat operations are made by simulation and low voltage experiments. The charging times are within 2.5 ms and the reverse current keeps 1.2 to 1.7 times over the fault current under arbitrary conditions. Di/dt at current zero is reduced by 80% under 30% of rated interruption capacity. Flexible capacitor charge experiments are consistent with the simulation design. The superconducting tapes can recover within 300 ms to support repeat operations. [ABSTRACT FROM AUTHOR]

One of the main challenges in the protection of the Inverter-Based Microgrids (IBM) is fault detection. Inverter-based resources have limited fault current; they also adopt different control schemes which make their fault current analysis and estimation more complex. These features make the traditional protection schemes inapplicable in IBMs. In this paper, two parameters are introduced and a protection scheme is proposed based on the introduced parameters to protect feeders and Distributed Generators (DGs) in IBMs. In the proposed scheme, in each sampling window, the last samples of the current waveform are predicted and the difference between the actual samples and the predicted samples are obtained; the voltage phase angle shift between the present and the past sampling windows is also computed; using these parameters and by introducing a new relay characteristic based on Mahalanobis distance the fault is detected in IBM. The effectiveness of the proposed protection scheme is verified through the simulation and experiment results. [ABSTRACT FROM AUTHOR]

Penetration of DC networks is rapidly increasing in modern power systems. As transient behavior of DC grids is different from that of AC ones, AC grid protection schemes might not be applicable to protect DC networks. Exact fault location is vital for protection of DC networks to reduce repair cost and achieve fast power recovery. This paper proposes a novel topology independent multi-terminal DC scheme to identify fault section and location for DC transmission systems. Voltage and current signals measured at the terminals are analyzed by the least squares error (LSE) algorithm. Then, the proposed scheme uses low frequency components of the signals to locate DC faults offline. Unlike some other methods, it does not require sophisticated sensors and hardware to capture very high frequency content of the signals. Hence, the proposed scheme can be implemented in practice without additional measuring infrastructure. The performance of the proposed scheme is evaluated under various fault conditions for different topologies of DC networks in both overhead lines and cables. Numerous simulations carried out demonstrate that the proposed scheme is quite accurate and provides excellent performance under different fault resistances, sections, and locations. [ABSTRACT FROM AUTHOR]

Optimal protection coordination is usually solved for the original network topology with all lines, loads, and generation intact. However, power grids may experience contingencies due to transient events, e.g., generation or line outages. Low fault currents of inverter-interfaced distributed generators (IIDGs) necessitate a sensitive and reliable protection scheme. This paper proposes a protection scheme for islanded microgrids powered by droop-based IIDGs. The protection scheme utilizes virtual impedance-fault current limiters to limit IIDGs fault currents and achieve protection coordination. A two-stage method for optimal protection coordination (OPC) of directional overcurrent relays (DOCRs) is devised. In Stage I, relays short-circuit currents are calculated. Then, constraints on the operation times of primary and backup DOCRs are formulated for the islanded topology and each possible topology following an N-1 contingency. Lastly, in Stage II, the OPC problem is formulated as a constrained nonlinear programming problem and solved to obtain the optimal DOCRs settings. A radial test microgrid that is part of a Canadian urban distribution system is used to ensure the success of the proposed OPC method. [ABSTRACT FROM AUTHOR]

The missing capability of DC fault current limitation is an inherent disadvantage in the typical half-bridge modular multilevel converter (MMC), which restricts its application in long-distance high voltage direct current (HVDC) systems. The full-bridge submodule (FBSM) and clamped double submodule (CDSM) topologies allow for fault current self-clearing, but also suffer from additional hardware cost and power losses. In this paper, an improved submodule topology utilizing the new reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed to improve system economy without compromising its performance. The operating principles and DC fault characteristics of the proposed topology are analyzed in details, including comparison with various topologies in terms of cost, losses, fault current clearing speed and thermal. Compared with the traditional CDSM topology, the proposed RBSM can clear DC faults faster with reduced cost of switching devices. A DC fault protection strategy for MMC-HVDC system is also presented. Simulation results under normal operating, permanent and transient fault conditions are carried out to verify the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a time-domain differential protection method based on the Bayes’ Theorem and on the current samples to determine the fault occurrence probability as a function of time. It also describes the theory involved in developing the proposed protection method when considering the differential protection of transmission lines. The authors performed fault simulations using an existing electrical system modeled in EMTP varying the fault type, phases involved, fault resistance, inception angle, and fault location, and carried out a sensitivity analysis regarding high impedance faults, current transformer saturation, noisy data, misalignments between terminal samples and power swings. The authors also tested the proposed method against actual fault events from four existing transmission lines of the Brazilian interconnected power system. All results indicate that the proposed solution is fast, accurate, secure, and dependable. [ABSTRACT FROM AUTHOR]

Inverter-Based Resources (IBRs), including Wind turbine generators (WTGs), exhibit substantially different negative-sequence fault current characteristics compared to synchronous generators (SGs). These differences may cause misoperation of customary negative-sequence-based protective elements set under the assumption of a conventional SG dominated power system. The amplitude of the negative-sequence fault current of a WTG is smaller than that of an SG. This may lead to misoperation of the negative-sequence overcurrent elements 50Q/51Q. Moreover, the angular relation of the negative-sequence current and voltage is different under WTGs, which may result in the misoperation of directional negative-sequence overcurrent element 67Q. This paper first studies the key differences between the WTGs and SG by comparing their equivalent negative-sequence impedances with SG's. Then, simulation case studies are presented showing the misoperation of 50Q and 67Q due to wind generation and the corresponding impact on communication-assisted protection and fault identification scheme (FID). The impact on directional element is also experimentally validated in a hardware-in-the-loop real-time simulation set up using a physical relay. Finally, the paper studies the impact of various factors such as WTG type (Type-III/Type-IV) and Type-IV WTG control scheme (coupled/decoupled sequence) to determine the key features that need to be considered in practical protection studies. The objective is to show potential protection misoperation issues, identify the cause, and propose potential solutions. [ABSTRACT FROM AUTHOR]

The existing Electromagnetic Time Reversal (EMTR)-based fault location methods generally leverage the features (e.g., energy) of the signals simulated in the EMTR reversed-time stage (relative to the direct-time stage wherein a fault occurs and its originated transient signals are measured). This paper presents for the first time an integrated time-frequency analysis that identifies the similarity between the signals respectively present in the direct time and in the reversed time. It is demonstrated that the fault current observed at the true fault location exclusively behaves as a quasi-scaled copy of the time-reversed back-injected transient current, such that, the fault location can be identified through a similarity assessment. In this respect, the paper proposes calculating a cross-correlation metric to quantitatively represent the level of similarity between the back-injected transient signal and the fault current signal simulated at the guessed fault locations. The similarity characteristic and the fault location performance of the proposed cross-correlation metric are validated first through simulation case studies based on the IEEE 34-bus test distribution feeder, and then using a pilot test wherein a live medium-voltage radial distribution network was subject to realistic fault occurrences. It is demonstrated that the proposed similarity metric is applicable to locating various types of faults and is robust against uncertainties like fault impedance and fault inception angle. [ABSTRACT FROM AUTHOR]

This paper deals with the modeling, hardware results and model validation by measurements of a VSC assisted resonant current (VARC) dc circuit breaker (CB) and the application within a future network by simulation. The newly emerging VARC dc CB can be used as a solution for the protection of offshore multi-terminal HVDC (MTDC) grids. In this paper, the proposed VARC dc CB is modeled in detail in a PSCAD environment, by taking into account dielectric strength of the vacuum gap, high-frequency current quenching ability and parasitic components. The PSCAD-model is then verified by data from the testing of a 27 kV VARC dc CB prototype with maximum current interruption capability of 10 kA. Additionally, the initial transient interruption voltage and current slope at zero-crossing during the interruption are analyzed. With respect to scaling to a higher voltage level, three types of series connected modules are presented and the performances are compared. The performance of the series connected modules is simulated in a model of a 4-terminal HVDC grid. The obtained results validate the VARC dc CB as a promising solution for the dc fault isolation in MTDC grids. [ABSTRACT FROM AUTHOR]

Closed-form determination of fault current limiter (FCL) impedance for symmetrical faults was reported previously using a mathematically rigorous method. In this paper, extensions of the method to asymmetrical faults are presented. Single line-to-ground faults and line-to-line faults are studied. As shown in this paper, although the material corresponding to asymmetric faults use the same basic concepts described before, the different nature of asymmetrical faults and application of symmetrical components theory lead to a different formulation. Also, the graphical representation of asymmetrical faults is as contour plots instead of the circle diagrams for three-phase faults. A three-bus and the IEEE 39-bus systems are used to illustrate the virtues of the method for the proper selection of FCLs impedance. Results demonstrate that the FCL designed, as shown in this paper, works properly for asymmetrical faults. The new formulation and graphical representation for asymmetrical faults are compatible with traditional power system short-circuit analysis software. An example with both symmetrical and asymmetrical faults is presented to illustrate how a full FCL impedance design can be achieved with the method. [ABSTRACT FROM AUTHOR]

In this part of the paper (Part II), available technical solutions to minimize or prevent wildfires caused by power networks are reviewed in more detail. These methods include fundamental changes to power system equipment, periodic checkups and maintenance, identification of faults via voltage/current waveforms, changes to protection and relaying settings and coordination, and installation of new power system apparatus. The strengths and drawbacks of each method are discussed. The discussion section brainstorms some future possible solutions that smart-grid technologies can enable. The paper concludes that there has neither been enough research in universities nor enough investment by industry to develop viable preventive solutions for wildfires that initiate from the daily operation of electrical power grids. This, in the authors’ opinion, is the crucial time for investment in research and development to tackle the lethal wildfire problem while electric power networks offer “the lowest hanging fruits to pick.” [ABSTRACT FROM AUTHOR]

This two-part paper presents a method to mitigate half-cycle saturation of transformers caused by monopolar operation of neighboring HVDC transmission lines while keeping the ability to detect the zero-sequence fault currents (ZSFC) when ground faults occur. Part I of this paper has presented the mitigation principles and device design of the proposed neutral current blocking switch. In Part II, the performance of the proposed method to permit the circulation of zero-sequence current is investigated. An operation strategy is proposed that simultaneously allows the mitigation of half-cycle saturation and the detection of ZSFC. Simulations on a widely-used 500 kV system show that the proposed mitigation technique, using a sub-synchronous switching frequency (no higher than 30 Hz), can effectively mitigate the half-cycle saturation while allowing the circulation of ZSFC. The novel mitigation method exploits the characteristic differences between half-cycle saturation (dc) and asymmetric faults (ac). The method provides an implementable solution to the dc-bias phenomenon because it delivers concurrently dc-bias mitigation, minimal impact on ground fault detection, and no switching stresses on the power electronic switches. The proposed technique can also be applied to the mitigation of geomagnetically induced currents. [ABSTRACT FROM AUTHOR]

Harmonic blocking is usually applied by converter transformer differential protection to prevent protection mal-operation during an inrush condition, but it may incorrectly block the protection during an internal fault. This paper first makes an in-depth analysis on factors that lead to differential protection failure to trip for converter transformer internal faults. The main factor responsible for the protection failure to trip is half-cycle saturation of the converter transformer core, which results from the dc component in the fault current. This suggests that harmonic blocking may not be suitable for differential protection of converter transformers to identify inrush conditions. In this regard, this paper proposes a novel method using mathematical morphology to effectively discriminate between the conditions caused by inrush and internal faults. This method implements the waveform symmetry criterion and improved morphological gradient criterion to distinguish between these two conditions. The effectiveness of the proposed method is evaluated based on extensive simulation, and the presented results show that the proposed method can ensure operation for all types of internal faults. Additionally, this method improves the accuracy of inrush identification, even in extreme cases, such as sympathetic inrush and inrush with current transformer saturation. [ABSTRACT FROM AUTHOR]

This paper provides a pragmatic solution to the challenge of testing fault current interruption of high-voltage direct current (HVDC) circuit breakers (CBs). The critical parameters in the design of a test circuit capable of supplying the necessary stresses: current, energy, and voltage (both during and after interruption) are discussed. In addition, a practical implementation of a test circuit based on ac short-circuit generators operated at low power frequency, which is capable of testing the current interruption performance of the proposed technologies of HVDC CBs, is discussed. Tests validating the proposed method and circuit have been conducted on a prototype of an HVDC CB and the test results are presented. Since the performance of some technologies of HVDC CBs can depend on the magnitude of the interrupted current, four test duties are defined and demonstrated in the paper. Moreover, testing of HVDC CBs using ac short-circuit generators poses new challenges, such as the application of dielectric dc stress after current interruption and the protection of both the test-object as well as the test-circuit components when the HVDC CB fails to interrupt. Methods to overcome these challenges are developed and practically demonstrated in a test laboratory. Finally, taking into account the available resources of the author's test laboratory, the capability to test multiple series-connected modules of different technologies of HVDC CBs is verified and example cases are demonstrated. Six short-circuit generators (13 500 MVA @ 50 Hz) and up to ten step-up transformers (up to 550 kV) were actually used. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) are vulnerable to DC short-circuit faults. Analytical estimation of the AC and DC short-circuit currents in the AC in-feed steady-state stage is essential to reveal fault mechanisms and design protections. However, the nonlinearity of the MMC has brought significant difficulties to the calculation. This paper proposes a novel analytical calculation method for the steady-state AC and DC short-circuit currents. First, various working modes of the MMC in the AC in-feed stage are specified, and the relations between the arm current and the short-circuit current in each mode are studied. Subsequently, the arm current is divided into multiple sub-intervals, and the analytical expressions of the steady-state AC and DC fault current are deduced by solving the arm current in the sub-intervals one by one. Moreover, the derived expressions are further optimized considering the resistive-inductive (R/X) characteristic of AC grids, making them applicable for various scenarios. These analytical expressions intuitively show the relations between the system parameters and the short-circuit currents, thus can guide the rating and tuning of protection devices and power equipment. Finally, the effectiveness of the derived expressions is verified, and the influences of the system parameters on the fault currents are discussed. [ABSTRACT FROM AUTHOR]

Phasor-based differential protection is widely used as the main protection function of the power transformer due to its reliability and ability to discriminate internal from external faults and inrush currents. However, these methods present some delays due to phasor convergence during the fault occurrence and can fail during challenging situations, such as transformer energizations with low second-harmonic content and turn-to-turn and turn-to-ground internal faults. This paper proposes a novel time-domain power transformer differential protection based on Clarke and wavelet transforms with only one differential unit and with automatic setting to be used in any power transformer. Considering both actual and simulation data, the performance validation reveals that the proposed method is efficient, ultra-fast, simple, and independent of the fundamental and harmonic components of the differential current. The method was also implemented in a real-time digital simulator to demonstrate its practical feasibility. [ABSTRACT FROM AUTHOR]

Electrical faults, which can occur at all voltage levels in an electricity supply system, are a health and safety risk. Multi-branch distribution networks represent a significant ongoing challenge for fault detection, with the greatest challenge being high impedance fault (HIF) detection. To date, research has focused on higher voltage levels, and fault monitoring sensors have traditionally only been installed in limited locations within the higher voltage networks. The main contributions of this paper are to characterize a high impedance fault (HIF) involving a tree branch and to experimentally verify the feasibility of giant magneto-resistive (GMR) sensors, located distant from the overhead lines, for fault detection. In a purpose-built 400 V physical simulation test facility, we have collected current and magnetic field data during HIF involving a tree branch. We have identified new characteristics in the early stages of this fault type, which persist for a reasonable length of time but are only observable when suitable signal processing techniques are applied. New detection schemes will, therefore, need to be developed to detect such faults. GMR sensors were found to be suitable for observing the characteristics of HIF, validating their potential use for fault detection. [ABSTRACT FROM AUTHOR]

This paper proposes a novel fast and accurate method to mitigate the decaying DC (DDC) component from the fault current signal. At the first stage, it starts to identify the DDC parameters by integrating six sub-cycle samples of current signal considering the symmetry feature of odd harmonics. By receiving the next samples, the estimation of DDC parameters is updated and improved. This procedure continues until the integral of a full cycle current signal is calculated. To improve the accuracy of phasor estimation procedure, in each stage, by subtracting the DDC component from original current signal, the discrete Fourier transform method is applied to estimate the fundamental phasor. Performance of the proposed method for different DDC parameters and fault conditions is verified through various test studies, and its robustness against harmonics, noise, off-nominal frequency, and multiple DDCs conditions is also investigated. Besides, to demonstrate the reliability of proposed method in terms of dependability and security, it is implemented on the phasor estimation block of a distance relay. Three types of data including mathematical, simulated, and real power system signals are used to evaluate the performance of proposed method. Obtained results confirm the desirable performance of proposed method in various operating conditions. [ABSTRACT FROM AUTHOR]

Synchronverters are inverters that imitate the behavior of synchronous generators to enhance the dynamics of renewable energy sources (RESs) powering microgrids. However, the synchronverter's inrush currents during faults could reach intolerable levels. Limiting the synchronverter's fault currents could obstruct protection relays from identifying faulted phase(s) during unbalanced faults, and hence, jeopardizing selective phase tripping (SPT). This paper unveils the root causes behind the deviation in phase selection that hinder SPT in microgrids powered by synchronverters. Virtual-impedance fault current limiters (VI-FCLs) are proposed for synchronverters to ensure accurate SPT by commercial relays and limit their sequence and DC inrush currents. Based on a short-circuit analysis, the positive- and negative-sequence VI-FCLs, as well as the active-to-reactive power ratio of synchronverters, are regulated to enable SPT and protect synchronverters from inrush currents. Simulation results using PSCAD/EMTDC ensure the effectiveness of the proposed control scheme in enabling reliable SPT in microgrids with synchronverters. The efficacy of the proposed scheme is assured by examining various fault types, a wide range of fault resistances, and the grid-connected and islanded modes. [ABSTRACT FROM AUTHOR]

Multi-inverter microgrid systems, particularly those with loop topology, offer higher power supply reliability and robustness compared to conventional radial distribution systems. In meshed systems, communication-less protection schemes have proved to be ineffective for multi-inverter microgrids due to bidirectional power flow, and limited and controlled fault currents generated by the voltage source converters interfacing the energy source to the network. This makes communication-assisted line protection schemes preferable for such systems despite the necessity for communication means. While these protection schemes are effective, their reliability depends much on the communication availability. This requires a back-up communication path in case the main one fails bringing up the cost issue that hinders their uptake. This paper proposes a novel and low-cost line protection based on directional blocking strategy that can operate as a main as well as a back-up protection to any protection scheme using communication means between the line terminals. As the main, it requires low-bandwidth communication system. As a back-up, it would share the same communication means with the main one and use those of the healthy lines when the faulted line's fails. Thus saving the cost of back-up communication system. [ABSTRACT FROM AUTHOR]

High Impedance Faults (HIFs) occur by the contact between an energized conductor and a high impedance surface. Due to the low fault current level, HIFs cannot be detected by conventional protection and there is no fully efficient solution to this problem. HIF detection methods often extract metrics using signal processing techniques, such as Fourier Transform, Wavelet Transform, Stockwell Transform, and Mathematical Morphology. However, these techniques are applied under specific conditions, which hinders comparative and critical analyses among them. Therefore, this paper presents a critical review of HIF detection methods based on the aforementioned techniques, and also shows a detailed investigation of the performance of the metrics commonly used with them. To do this efficiently, the authors proposed a set of assessment indices based on the ratio between the metrics’ characteristics and another one based on the repeating of the metrics features. The proposed indices revealed that some of these metrics fail to distinguish HIF from other typical occurrences in power distribution systems, and their performances are negatively affected by the fault location and by the existence of noise in the measurements. Additionally, the results showed a need to specify system conditions in which any HIF detection technique is valid. [ABSTRACT FROM AUTHOR]

The allocation of fault current limiters (FCLs) is increasingly challenging in transmission systems these days. Specifically, the utilized deterministic expected short-circuit fault (SCF) scenarios are prone to cause over-configuration of FCLs. Moreover, the well-established local switching framework (LSF) renders inappropriate FCL switching and may further harm the system safe operation. Aiming at the above deficiencies, a novel 5G-based centralized switch FCL (CSF) framework as well as a method to allocate such flexible FCLs optimally is proposed in this paper. In the proposed CSF, the FCLs are switched by a FCL dispatching (FD) model considering system security constraints of both fault current and voltage sags. By exploiting the fast communication capability of 5G network as well as an off-line fault scanning strategy, the FD model is enabled to give online FCL switching schemes to meet the fast requirement of power system protection. Moreover, considering the probabilistic characteristic of SCFs, a bi-level FCL allocation model is established, in which the upper-level model sites and sizes FCLs considering the installation and expected switching costs while the lower-level model determines the optimal switched FCLs under each specific SCF scenario. Finally, numerical results are provided to verify the proposed allocation model, including its defending effect against SCFs in terms of fault current limiting, voltage sags relieving, as well as its cost-effectiveness. [ABSTRACT FROM AUTHOR]

The exclusive fault behaviors of MMC-HVDC stations bring great challenges to the correct operations of distance relays. This paper presents a new zone I distance relaying scheme that can accurately calculate fault distance in the case of integration of MMC-HVDC system. The two calculation formulas of fault distance are derived from mathematical perspective and geometrical relationship of impedances, respectively. Phase angle of fault current is the key to calculate fault distance. In power system without MMC-HVDC stations, the existing method for solving this phase angle is based on two premises, that is, the positive- and negative-sequence current distribution factors are equal and real numbers. However, owing to the integration of MMC-HVDC system, aforementioned premises are both not true. Consequently, the existing method cannot obtain accurate phase angle of fault current. To solve this problem, the three solutions corresponding to three different types of asymmetrical faults are provided. The proposed scheme has the advantages of satisfactory immunity against fault resistance, applicable to various asymmetrical faults, and performing well under rectifier as well as inverter modes. The performance of the proposed scheme is evaluated by simulation results in PSCAD/EMTDC and compared with prior-art schemes. [ABSTRACT FROM AUTHOR]

Hybrid circuit breaker (HCB) has shown good performance for interrupting dc fault current. However, a massive number of IGBTs in series is needed. These will lead to high costs and significant difficulty in balancing IGBT dynamic voltage. This paper proposes a bidirectional hybrid circuit breaker based on a cascaded half-bridge submodule structure to reduce the overall costs and implementation difficulty of HCB. The number of IGBTs is reduced by 50%, and the operating speed is fast enough. A model of a four-terminal modular multilevel converter (MMC) system with a proposed hybrid circuit breaker in different stages is developed to describe the fault blocking process more clearly. The performance of the proposed HCB is validated and compared with other HCB structure through both theoretical derivation and time-domain simulation. [ABSTRACT FROM AUTHOR]

A DC system saturated core fault current limiter (DCSFCL) was proposed to limit the fast rising trend of fault current in HVDC system. However, traditional method to calculate and design the DCSFCL tend to neglect leakage flux around the permanent magnet (PM), leading to large calculation error and inappropriate design procedure. The novel contribution of this paper is that it proposed a modularization method to analyze the permeance of both PM and adjacent air. Hence, the leakage flux effect is considered properly and a more accurate permeance matrix can be derived in a pure mathematical way. In this case, DCSFCL can be calculated much faster than the FEA simulation program with a promising accuracy regarding fault limiting performance. More importantly, design flow of the DCSFCL and related PM biased devices was given as well. Calculation result shows that inductance value calculated by the proposed method has less than 1% error compared with fine meshed FEA simulation result and about 20% increase in accuracy compared with traditional method that neglects PM leakage flux effect. Prototype of the DCSFCL was also built and experimental tests were carried out to verify the correctness of the proposed method. [ABSTRACT FROM AUTHOR]

Medium voltage direct current (MVDC) power systems are in their early phase of development, but the lack of efficient and reliable DC circuit breakers is currently one of the most significant bottlenecks for widespread adoption of MVDC applications. Compared to protection devices in high voltage direct current (HVDC) systems, MVDC circuit breakers are expected to interrupt fault currents with higher rates of rise in more power-dense and more controllable structures. A hybrid approach with a piezoelectrically actuated fast mechanical switch in parallel to a solid-state circuit breaker is expected to meet the above requirements. A prototype of a 15 kV-class piezoelectrically actuated fast mechanical switch is presented in this paper. The prototype demonstrates an actuator opening time of 1 ms, a breakdown voltage of over 20 kV, and a continuous current rating of 500 A. After integrating the fast mechanical switch into a hybrid circuit breaker testbed, the fast mechanical switch was able to open within 1.5 ms and the fault was cleared within 5 ms. Therefore, piezoelectrically actuated fast mechanical switches can enable fast, reliable and controllable protection for various MVDC systems like electric ships, electric aircraft and microgrids that integrate distributed energy resources. [ABSTRACT FROM AUTHOR]

Directional, phase-selection, and distance elements of a relay are prone to misoperation in the presence of inverter-based resources (IBRs). To address these problems, modifications of relay elements as well as new control schemes for IBRs have been proposed in the literature. These methods focus mainly on addressing the misoperation of only one of the above relay elements. The available solutions that are based on a new control system focus only on the negative-sequence current loop. Thus, they work only for unbalanced faults. This paper proposes a comprehensive dual current control scheme for IBRs during all types of faults such that all of these relay elements operate correctly. The proposed method controls the IBR to operate as a voltage source behind a virtual impedance in the positive-sequence circuit, and a single impedance in the negative-sequence circuit, thereby emulating the phase angles of a synchronous generator's (SG's) fault current. The proposed method also maximizes the active, and reactive current generation of the IBR during faults, and emulates the incremental sequence current magnitudes of an SG. The proposed method does not require altering the relay elements. Moreover, correct operation of the relay elements is achieved regardless of the fault type, resistance, and location. The effectiveness of the proposed method is verified through not only simulation studies, but also hardware-in-the-loop testing of commercial relays. [ABSTRACT FROM AUTHOR]

Conventionally, the current flow control and DC fault protection issues of HVDC grids are supposed to be solved by the DC current flow controller (CFC) and DC circuit breaker (DCCB) separately, which may result in a high capital cost. This paper proposes a CFC topology with DC fault current limiting and interrupting capabilities. The topology and operating principle of the CFC are presented with theoretical analysis. The control strategies under normal and fault conditions are described. In order to reduce the use of IGBTs, an H-bridge inter-line CFC with fault current limiting capability is further proposed based on the proposed CFC. The proposed CFCs are tested in PSCAD/EMTDC. Simulation results show that the proposed two CFCs can effectively control the current flow of two lines during normal operation and limit and interrupt DC fault currents. [ABSTRACT FROM AUTHOR]

Protection coordination for the microgrid system in both islanded and grid connected modes is considered a challenge for microgrid operation. The variation in short circuit currents in each mode of operation, limitation of protection curves in the relays, and the need for fast and reliable communication are the main challenges tackled in research. Direction overcurrent relays are considered the main protection instrument for the microgrid. However, one protection setting for both (main and backup) operation does not provide a fast-operating time. On the contrary, the dependence on communication to maintain the proper backup protection operation is not a reliable solution for protection system. Therefore, this paper introduces a fast, reliable, and simple protection scheme for secure microgrid operation in both islanded and grid connected modes. In this context, one set of protection settings is optimized and used in both modes of operation. A protection setting consists of two time-dial settings and one pickup current setting for each relay. The proposed design technique minimizes the total operating time for both main and backup relays. As all protection functions are executed in the forward direction, no communication is needed among relays. The proposed scheme is tested and verified on a modified portion of IEEE 30 bus test system equipped with distributed generation units. A comparative analysis is carried out and the results demonstrate superior performance by the proposed scheme in comparison with the dual setting scheme with communication. [ABSTRACT FROM AUTHOR]

For modular multilevel converter (MMC) based DC grids, current-limiting reactors (CLRs) are mainly employed to suppress the fault current and provide boundary effects to detect internal faults. Thus, most existing protection schemes are highly dependent on the larger CLRs to guarantee high selectivity. However, in existing MMC based HVDC projects, the size of CLRs is restrained by the cost, weight, and system stability under normal state. Thus, boundary protections may fail to detect high-resistance faults and pole-to-ground faults under weak boundary conditions. To overcome these shortcomings, this paper proposes a fast and selective DC fault detection scheme independent of boundary components. The propagation characteristics of line-mode backward traveling-waves (TW) are analyzed to identify external and internal faults. The polarities of zero-mode backward TWs are employed to select faulted poles. The directional overcurrent based pilot protection is adopted as a complementary criterion to detect remote faults. The proposed method can be applied in MMC-HVDC systems with small CLRs that cannot provide strong boundary conditions. Besides, the detection speed is fast (less than 1.5ms). Moreover, it is robust to fault resistance and immune to noise. Various simulation results in PSCAD/EMTDC verifies the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

This paper proposes a new method to select single-line-to-ground (SLG) fault feeder in resonant grounding power distribution system based on compensation characteristic of extinction coil in different frequencies. The proposed method is insusceptible to the influence of device polarity reverse installation. Firstly, through analyzing the zero sequence equivalent circuit under a SLG fault, the difference of zero sequence current share in fundamental frequency and second-harmonic frequency is investigated. And then, according to the change of current share (CCS), fault feeder selection criterion and steps are established. Finally, numerous simulation tests demonstrate the effectiveness of the proposed method in identifying the faulty feeder or the faulty bus. Besides, its reliability is also verified by tests with different system parameters and different fault conditions. Specially, device polarity reverse installation tests and comparisons are also implemented, which shows the advantages of the proposed method in dealing with device polarity reverse installation. [ABSTRACT FROM AUTHOR]