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To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH $x2$ programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH $x2$ threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH $x2$ threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH $x2$ threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH $x2$ threshold cell–along with the symmetry of the mask- and field-programmable gate array logic cells–made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric. [ABSTRACT FROM AUTHOR]

In this paper, we describe a design of a mixed-signal circuit for an binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication [ABSTRACT FROM AUTHOR]

Field-Coupled Nanocomputing technologies have great potential to surpass CMOS technology because of their lower power consumption and higher device concentration. To ease the burden of placement and routing (P&R) problems for FCN circuits, many delicate two-dimensional clocking schemes have been proposed, upon which algorithms can solve the P&R problems more strategically. In this paper, we propose a two-level optimization strategy by using a genetic algorithm (GA) combined with an enhanced A* algorithm. Some circuit design requirements, such as clock synchronization, layout area, etc., are cleverly designed in the fitness value function of the GA. Numerical results demonstrate the effectiveness of the hybrid algorithm. In particular, compared to current tools, such as fiction and Ropper, the proposed algorithm can achieve an optimal solution with a higher success rate and a sizeable applicable circuit scale. In addition, the concept of design rule checking (DRC) was proposed in FCN and integrated into the algorithm, making the P&R results mapping from gate-level to cell-level more smoothly. Besides, the number of cross wires is significantly reduced, and the distribution of IO ports can be more effectively controlled. [ABSTRACT FROM AUTHOR]

The performance of nanoscale semiconductor technologies has become susceptible to high temperatures and aging phenomena. While guard-bands have conventionally been used to combat degradation-induced timing violations, approximations have recently been leveraged to compensate for degradations in lieu of adding timing guard-bands, without a loss in performance. However, only simple approximation techniques such as truncation have been considered in prior work. In this paper, a wide range of approximate arithmetic circuits including adders and multipliers using various sophisticated approximation techniques are investigated to cope with aging- and temperature-induced degradations. To this end, approximate circuits are first characterized for their delay increase under degradations. With this, we then determine the approximation level required to compensate for guard-bands under different degradations. Degradation-aware logic synthesis results show that the simple use of truncated arithmetic circuits leads to a higher quality loss compared to using other approximate circuits. However, a truncated multiplier has the lowest error distance towards a reliable operation in 10 years. The approximate multipliers with configurable error recovery are most suitable when the level of degradation is higher, e.g., at a temperature of 70 °C. The characterization of degradation at the circuit level is then used for design exploration at the architecture level without the need for further gate-level simulations. For three different image processing applications, experimental results show that guard-bands can be mitigated while maintaining an output result with a high visual quality. [ABSTRACT FROM AUTHOR]

Single-electron transistors (SETs) exhibit a unique characteristic of Coulomb oscillation which can find many digital applications with area efficiency. More specifically, both MOS and SET devices can be used to implement XOR gates with almost the same area costs regardless of the number of their inputs, outperforming pure CMOS solutions. As multiple-input XOR gates are abundant in the finite field polynomial multiplication which represents the most frequent computation in elliptic curve cryptosystem, hybrid SET-MOS technology can substantially reduce the area cost for this application. This paper presents polynomial multiplication architectures with hybrid SET-MOS transistors and explores Karatsuba-algorithm based multiplication for further area optimization. Simulations show that the proposed hybrid SET-MOS implementations can typically provide around 37% savings in terms of gate count compared to their traditional CMOS counterparts. [ABSTRACT FROM AUTHOR]

This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads ($\text{C}_{\mathrm {L}}$) and operating frequencies (${f}_{\mathrm {s}}$). The circuit consumed a power between 610 $\mu \text{W}$ and $850~\mu \text{W}$ across the measured deadtime ranges while $\text{C}_{\mathrm {L}} =12$ pF, $\text{V}_{\mathrm {dd}} =3.3$ V, and $\text{f}_{\mathrm {s}}=200$ kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of $150\mu $ m $\times 260\mu \text{m}$. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum $\text{T}_{\mathrm {DLH}}$ and optimal $\text{T}_{\mathrm {DHL}}$ at $\text{I}_{\mathrm {Load}} =25$ mA is improved by 12% compared to a converter with a fixed deadtime of $\text{T}_{\mathrm {DLH}} =\,\,\text{T}_{\mathrm {DHL}} =12$ ns. [ABSTRACT FROM AUTHOR]

By their very nature, Spin Waves (SWs) excited at the same frequency but different amplitudes, propagate through waveguides and interfere with each other at the expense of ultra-low energy consumption. In addition, all (part) of the SW energy can be moved from one waveguide to another by means of coupling effects. In this paper we make use of these SW features and introduce a novel non Boolean algebra based paradigm, which enables domain conversion free ultra-low energy consumption SW based computing. Subsequently, we leverage this computing paradigm by designing a non-binary spin wave adder, which we validate by means of micro-magnetic simulation. To get more inside on the proposed adder potential we assume a 2-bit adder implementation as discussion vehicle, evaluate its area, delay, and energy consumption, and compare it with conventional SW and 7 nm CMOS counterparts. The results indicate that our proposal diminishes the energy consumption by a factor of $3.14 \times $ and $6 \times $ , when compared with the conventional SW and 7 nm CMOS functionally equivalent designs, respectively. Furthermore, the proposed non-binary adder implementation requires the least number of devices, which indicates its potential for small chip real-estate realizations. [ABSTRACT FROM AUTHOR]

Stacked MOS power amplifiers (PA) are commonly used in SOI nodes but also have the potential to be realized in bulk CMOS nodes. In this paper they are analyzed in millimeter wave regimes. The study focuses on the key limiting factors and in particular the optimum number of transistors from which the key performance parameters such as maximum possible operating frequency, output power, and efficiency are achieved. Based on the analysis, design trade-offs of stacked MOS PAs are presented. The frequency dependency of the optimum load presented to each stack is analyzed to express the overall performance of the mentioned PA topologies as a new optimization method. Additionally, it is shown how the optimal load variations translate into amplitude-to-amplitude/phase (AM-AM/PM) conversion distortions. The validity of the analysis is examined against simulations. The simulations are performed based on 8M1P CMOS 28nm technology and electromagnetic simulations in ADS Momentum. [ABSTRACT FROM AUTHOR]

Recurrent Neural Networks (RNNs) have emerged as one of the most popular neural networks for processing time-series problems, widely used in machine translation, automatic speech recognition, and other natural language processing applications. However, conventional RNNs suffered from vanishing and exploding gradients, resulting in poor network performance in applications with long-term input information. As a variant of RNN, Long Short-Term Memory (LSTM) had been proposed to tackle this issue. Nevertheless, at the same time, LSTM introduces gating units and many additional parameters, which makes it challenging to be implemented directly on resource-limited platforms, such as Field Programmable Gate Arrays (FPGAs). This work first investigated the overall maximum achievable compression rates of different gating units and their correlations. Then, Gating Units Level Balanced Compression (GBC) strategy is proposed. After Top- $k$ pruning, the proposed GBC strategy can attain a compression rate of $36.6\times $ for LSTM. Further, the theoretical analysis indicates that for the existing gating units level LSTM compression variants, the GBC strategy still has further potential for compression. A complementary compression of the GBC strategy is performed on the existing coupled-gate LSTM to verify the analysis. Experimental results show that GBC achieves an additional $32\times $ (overall $42.7\times $) compression rate with negligible accuracy loss. Finally, hardware experiments conducted on Xilinx ADM-PCIE-7V3 FPGAs also demonstrate that the accelerator designed in this paper achieves an improvement of 7.4%-191.5% in energy efficiency compared to the state-of-the-art designs. [ABSTRACT FROM AUTHOR]

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed. [ABSTRACT FROM AUTHOR]

A 3D architecture made up of a CMOS layer combined with a 3D stack of bipolar memristor crossbar arrays provides an innovative approach to hardware support for utilizing the strength of CMOS combined with the strength of memristors. Memristors have been evaluated for implementing a broad spectrum of applications such as memory, computations, hardware-based security primitives, cryptography, etc., and numerous studies have shown that memristors are desirable candidates for such applications. This paper proposes a novel 3D memristive crossbar architecture (i.e., a stack of memristive crossbar arrays built on top of CMOS substrate) with a specific focus on the way of connecting the crossbar arrays to the CMOS layer. The proposed architecture is configurable and allows restructuring crossbar arrays and creating 1D arrays with adjustable sizes. The proposed architecture enables parallel and pipeline computations where data can move or be processed in planes perpendicular to the stacked crossbar arrays. In addition, the proposed architecture is scalable meaning that stacks of crossbar arrays can be connected without additional overhead. This paper shows examples of implementing a full adder, a 4-bit look-ahead carry generator, and an 8-bit multiplexer. Simulations and area, delay, and power analysis demonstrate the behavior of the proposed 3D circuit. [ABSTRACT FROM AUTHOR]

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18- $\mu \text{m}$ partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant- $g_{m}$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/°C, and a variability $(\sigma /\mu)$ of 1.66 %. Then, two 4T+1R $\mu \text{A}$ -range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09- $\mu \text{A}$ (resp. 0.99- $\mu \text{A}$) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/°C (resp. 290-ppm/°C) TC, and a 0.87-% (resp. 0.65-%) $(\sigma /\mu)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations. [ABSTRACT FROM AUTHOR]

The divider is one of the most complex hardware units in Stochastic Computing (SC); even though several new designs have been presented to reduce the computation latency of the conventional divider, all of them still require a considerable number of clock cycles. Moreover, they incur in low performance due to the employed arithmetic computational scheme. In this paper, a Delta Sigma Modulator (DSM) based stochastic divider is proposed. As an entirely digital circuit, the proposed divider offers the best computation latency and accuracy over all existing stochastic dividers found in the technical literature (with a typical reduction between 66.8% and 96.9% in the number of clock cycles and a reduction from $10^{\mathrm {-3.4}}$ to $10^{\mathrm {-3.9}}$ in the average mean square error for a 10-bit resolution). An SC-based Neural Network (NN) is considered as an initial case study to evaluate the advantages of the proposed design in an emerging application; results show that the proposed divider enables an SC-based NN to achieve a higher classification accuracy and hardware efficiency than existing designs. To show the flexibility of the proposed divider design, its application to Sobol-based sequences is also presented; also in this case, its superiority over other designs is confirmed. These features make the proposed design very attractive for hardware-constrained platforms; moreover, such a novel design approach that incorporates ideas from analog/mixed signal circuit design into a digital circuit design, can motivate other researchers to design efficient SC designs using similar schemes. [ABSTRACT FROM AUTHOR]

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- $\mu \text{m}$ standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved $\sim 1.24\times $ more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%. [ABSTRACT FROM AUTHOR]

This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfOx memristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between $5.2\times - 17.3\times $ , which also accounts for intermediate voltage buffering to alleviate the memristive loading problem. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of an oscillator-doubler architecture which is used to generate THz signals. In this architecture, the doubler obtains the optimum fundamental-frequency load impedance for second harmonic generation without causing problems related to instability. The oscillator creates voltages close to the optimum voltage condition, which leads to maximum power being delivered to the doubler connected to the oscillator tank. Compared to a signal generator composed of an oscillator and a conventional doubler with short-circuit load at the fundamental frequency, the proposed circuit has higher output power and DC-to-THz conversion efficiency. Based on this architecture, a 0.3-THz signal generator is designed in 40-nm CMOS. In this 0.3-THz signal generator, an inductor-sharing configuration is proposed to increase the transistor size in the cross-coupled oscillator, thus increasing the power density of the signal generator. Besides, the impact of the doubler fundamental-frequency load impedance on the conversion gain of the doubler is introduced. Also, a method of suppressing the unwanted mode in the cross-coupled oscillator is proposed. The output of this circuit is radiated through on-chip antennas. The measured radiated power and the DC-to-THz efficiency of the chip are -3.8 dBm and 0.37%, respectively, with an output frequency tuning range of 4.8%. [ABSTRACT FROM AUTHOR]

This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near- $V_{{\text {DD}}}$ negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the high dv / dt slew rate of $V_{\text {X}}$ when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of $V_{\text {X}}$ , thus the near-optimal zero-voltage switching can be achieved with deviation < 3 ns. The GaN driver is implemented with a 0.18- $\mu \text{m}$ BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area. [ABSTRACT FROM AUTHOR]

In the Mesochronous Pipeline (MP), the clock period is the maximal of differences between the maximum/minimum delays of all stages. This value is less than the maximum delay between the memory elements, so MP is operating faster than the conventional pipeline (CP). To take full advantages of MP, in this paper, Automated Mesochronous Pipeline Scheduler (AMPS) for high performance digital circuits, is proposed which provides all allowed partitioning options generated by register allocation procedures obtained with varying maximum delay differences of stages. This allows a designer to select from design space produced by AMPS based on the desired specification. Unlike the traditional MP, AMPS utilizes automated scripts to extract the timing characteristics of the synchronizers and gates. This enables a designer to explore trade-offs between latency, power, and frequency. To evaluate our toolset, an 8-bit Carry Increment Adder (CIA), a 4-bit Binary-Coded Decimal (BCD) adder, a 4-bit ALU, and a set of circuits from ISCAS85 and ISCAS89 benchmarks are considered. All circuit level simulations are performed in the 65nm CMOS standard technology node. AMPS improves the frequency for its best solutions about 127.94% (on average) in comparison to the conventional pipeline scheme. [ABSTRACT FROM AUTHOR]

This paper presents a discrete-time low-noise amplifier for miniaturized sensor nodes. Such amplifier achieves a noise efficiency factor of 1.01 and a power efficiency factor of 1.63, improving the noise efficiency of an analog front-end. The proposed preamplifier employs discrete-time parametric amplification by modulating the capacitance of a MOS varactor. The sampling noise is minimized by adopting a high oversampling ratio of the input voltage, leading to an input-referred noise of 520 nVrms in a 1 kHz bandwidth. Also, the power consumption is reduced by using a 34-phase stepwise charging technique. The multiphase soft-charging technique is implemented using multiple time-interleaved cells and allows to significantly reduce the current consumption without introducing any significant penalty in terms of additional noise or area occupation. A two-stage parametric amplifier is introduced to provide higher gain, and suppress the noise contribution of the following amplifier chain. The proposed two-stage complementary preamplifier is followed by a third continuous-time stage, that employs a current-reuse inverter-based architecture. The contribution to the total noise efficiency factor of such amplifier is attenuated by the gain of the previous two-stage parametric preamplifier. As a result, the third stage provides gain programmability, while degrading the NEF of the entire chain by less than 10%. [ABSTRACT FROM AUTHOR]

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively. [ABSTRACT FROM AUTHOR]

In recent decades, the performance of binary computers has escalated through transistor scaling. However, due to the impotent forecasts of transistor scaling, ternary systems are regaining attention. Among many ternary device candidates, a passive device called memristor that is based on resistance switching is considered a good candidate when integrated with MOSFETs. Therefore, in this paper, we design various terna-ry logic based on memristors and MOSFETs from primitive logic to sequential logic and perform a thorough diagnosis for circuit design. We highlight design issues that should be resolved (e.g., signal distortion and high static current) and present practical solutions such as “Strength Design.” Then, we report a proper design methodology of sequential circuits considering the spike phenomena of memristor-based gates. We present 16 novel ternary logic cells and circuitry, including the design of the first balanced ternary full-adder (TFA) and memristor-based ternary pulsed-latch (MTPL). By our TFA, we emphasize that it is possible to design the most practical ternary circuits using memristors and MOSFETs. Our TFA uses 97 transistors and 87 memristors, which is the most reasonable TFA design that has the highest potential to be implemented in the near future. Besides, the proposed MTPL uses 16 transistors and 10 memristors, and it occupies only 72.7% of the silicon area, compared to the master-slave ternary flip-flop. [ABSTRACT FROM AUTHOR]

Recently, integrating ferroelectric materials with nanotransistors such as carbon nanotube field-effect transistors (CNTFETs) has opened new doors for demonstrating a new generation of ultra-miniature circuits and systems. Utilizing the negative differential resistance effect in negative capacitance CNTFETs (NC-CNTFETs) has spurred the efforts for designing ultra-compact ternary circuits and systems similar to their binary structures. This paper presents an ultra-efficient ternary image edge detection hardware using NC-CNTFET technology. The proposed hardware is endowed with a noise reduction circuitry to mitigate the noise effects. Using four $1\times 3$ kernels and concatenating the image pixels, the proposed ternary hardware has been designed using only 50 transistors. The proposed ternary hardware at the circuit level shows, on average, 74% improvements regarding power delay-product (PDP) compared to the CNTFET-based counterparts. Our comprehensive simulations indicate that the proposed NC-CNTFET-based hardware shows a 40% improvement in data loss, 2.2 times improvement in performance ratio, and 1.14 times improvement in Pratt’s figure-of-merit, respectively, compared to the related designs. Our results accentuate that the proposed NC-CNTFET-based ternary hardware is a breakthrough achievement in demonstrating ultra-efficient and noise-immune ternary image processing circuits beyond the conventional binary counterparts. [ABSTRACT FROM AUTHOR]

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required. [ABSTRACT FROM AUTHOR]

In this paper, we revisit Boole’s expansion theorem to propose a new synthesis method for implication logic circuits based on memristors. By rewriting the sum-of-products form of Boole’s expansion theorem in terms that are best suited for the implication logic, we develop a generalized rule to derive the sequence of operations needed to realize any logic function written in the classical AND-OR form. The proposed method leverages on multi-input operation, minimizing both the number of steps required to compute a given Boolean function and the number of memristors involved. Moreover, it allows using well-established methods of logic circuit optimization like binary decision diagrams, Karnaugh maps, and heuristic algorithms, that are already implemented in commercial CAD software. The proposed method allows a fair comparison between the performance of CMOS and implication logic implementations of the same logic function under the same degree of optimization, and is shown to outperform existing approaches. Possible device-circuit co-design strategies to optimize circuit performance are finally discussed. [ABSTRACT FROM AUTHOR]

In this paper, passive-less fully-digital operational transconductance amplifiers (DIGOTA) for energy- and area-constrained systems are modeled and analyzed from a design viewpoint. The digital behavior of DIGOTAs is modeled as an equivalent small-signal differential-mode circuit with zero bias current, and a common-mode feedback loop operating as a self-oscillating threshold sampler. Such continuous-time equivalent circuits are used to derive an explicit model of the main performance parameters that are generally adopted to characterize OTAs. This provides an insight into circuit operation and allows to derive practical guidelines to achieve a given design target. Among the others, an explicit model is derived for the DC gain, the frequency response, the gain-bandwidth product, the input-referred noise, and the input offset voltage. The models are validated via direct comparison with multi-die measurement results in CMOS 180 nm. From an application viewpoint, the voltage (power) reduction down to 0.25 V (sub-nW) uniquely enable direct harvesting (e.g., with solar cells), suppressing any intermediate DC-DC conversion stage. This further enhances the area efficiency advantage of DIGOTA stemming from its fully-digital nature, making it well suited for cost-sensitive and purely-harvested systems. [ABSTRACT FROM AUTHOR]

Approximate computing is an efficient approach for reducing computational costs. This method involves a trade-off between computational accuracy and the circuit’s power consumption, delay, and area. However, the accuracy requirements may differ for different applications. In some situations, precise results are required. Therefore, this paper proposes an accuracy-configurable radix-4 adder (ACRA), which uses the power gating technique to turn on or turn off the partial logic gates of an adder element dynamically to compute accurate or approximate results. When the ACRA operates in the approximate mode, the partial sum of one adder element is modified to reduce the error distance between the approximate and accurate results. A comparison of the ACRA with two state-of-the-art accuracy-configurable adders indicated that the ACRA achieved the best trade-off between the power–delay product and computational accuracy. In addition, in the image processing experiment conducted in this study, under half-approximate computation, the peak signal-to-noise ratio of the ACRA was less than 1 dB and its structural similarity index measure was maintained above 0.99. These results are superior to those obtained for other accuracy-configurable adders. [ABSTRACT FROM AUTHOR]

A highly linear active mixer in Gallium Nitride on Silicon (GaN-on-Si) monolithic microwave integrated circuit (MMIC) technology, operating in Ka-band for radar applications is introduced. It exhibits a local oscillator (LO) balanced topology of gate-pumped mixers based on high-electron mobility transistors (HEMT) and operates in down-conversion mode. Its design principles and the theoretical foundation of its linearity features resulting from both the high power handling capability of GaN-on-Si HEMTs and the corresponding high applied LO level are presented. An extensive characterization based on excitation of a prototype by broadband continuous wave signals and frequency modulated continuous wave signals validates both the analytical treatment of its linearity and the design of the prototype of the mixer. In the 35–40 GHz operating band, this prototype exhibits a state-of-the-art input referred third order intercept point that reaches 39.1 dBm, and a maximum input referred second order intercept point of 39.4 dBm, with a corresponding conversion gain of −5.2 dB, and LO level of 24 dBm. [ABSTRACT FROM AUTHOR]

In-memory computing using emerging technologies such as Resistive Random-Access Memory (ReRAM) has been proposed as a promising substitute for future computing applications to address the ‘von Neumann bottleneck’. Multiplication is the key component for inner product computation in every digital signal processing (DSP) application and the complexity of multipliers increases greatly with bit-width. Distributed arithmetic (DA) using look-up tables and adder-shifter module has been proposed for inner product computation to achieve multiplier-less efficient DSP architectures, particularly when one of the vectors is a constant and known in advance. Due to the memory wall, DA can be made furthermore latency and energy-efficient when implemented ‘in memory’. In this work, for the first time, we propose two design techniques to compute inner product completely in memory using DA. This is accomplished by storing the precomputed look-up table contents in a ReRAM array and implementing adder-shifter module also in the same array. The adder-shifter is implemented in memory using majority gates which are in turn realized as READ operations in the memory array. Two methods of mapping: latency-optimized and area-optimized and their comparison in terms of latency and area are presented. The proposed method-1 achieves $\approx 60$ % energy savings compared to CMOS and the proposed method-2 achieves 10.59 times higher throughput compared to CMOS. [ABSTRACT FROM AUTHOR]

One of the major barriers that CMOS devices face at nanometer scale is increasing parameter variation due to manufacturing imperfections. Process variations severely inhibit the reliable operation of circuits, as the operational frequency at the nominal process corner is insufficient to suppress timing violations across the entire variability spectrum. To avoid variability-induced timing errors, previous efforts impose pessimistic and performance-degrading timing guardbands atop the operating frequency. In this work, we employ approximate computing principles and propose a circuit-agnostic automated framework for generating variability-aware approximate circuits that eliminate process-induced timing guardbands. Variability effects are accurately portrayed with the creation of variation-aware standard cell libraries, fully compatible with standard EDA tools. The underlying transistors are fully calibrated against industrial measurements from Intel 14nm FinFET in which both electrical characteristics of transistors and variability effects are accurately captured. In this work, we explore the design space of approximate variability-aware designs to automatically generate circuits of reduced variability and increased performance without the need for timing guardbands. Experimental results show that by introducing negligible functional error of merely $\boldsymbol {5.3 \times 10^{-3}}$ , our variability-aware approximate circuits can be reliably operated under process variations without sacrificing the application performance. [ABSTRACT FROM AUTHOR]

The appealing property of low area, low power, and high bit error tolerance has made Stochastic Computing (SC) a promising alternative to conventional binary arithmetic for many computation intensive tasks, e.g., convolutional neural networks (CNNs). However, current SC-based CNN accelerators suffer from the intrinsic computation error and exponentially growing latency. In this work, we optimize both the architecture of SC multiply-and-accumulate (MAC) unit and the overall acceleration strategy of CNN accelerator to favor SC. A low-complexity bit-stream-extending method is proposed to suppress the computation error of SC and ensure the trained fix-point model can be deployed into SC-based hardware without fine-tuning. Besides, distribution-determined partition scheme is developed to design hybrid stochastic-binary computing (SBC) MAC unit which boosts the processing of bit streams at a minimum overhead. For the overall accelerator, the SBC-based MAC array is extended to reuse hardware resources and improve throughput, since the judiciously chosen loop unrolling strategy can better benefit SC operations. The proposed CNN accelerator with extended SBC-MAC array is synthesized and validated using TSMC 28nm CMOS on several representative CNNs, targeted at ImageNet dataset. Compared with precise binary implementation, our proposed design gains 44% area reduction and 50% power saving but induces only 4% additional computation latency and 0.5% accuracy degradation. [ABSTRACT FROM AUTHOR]

This work presents a tail-less fully differential bulk-driven transconductance amplifier without using a common-mode feedback (CMFB) circuit. The proposed amplifier employs two P-type and N-type current mirrors to form two self-biasing positive feedback loops resulting in a double transconductance. The bulk terminals of the P-type current mirrors are used as the input nodes to provide a high input dynamic range. The diode-connected topologies of the current mirrors adaptively bias other transistors to cover the lack of the CMFB circuit. To ensure stability, additional current sources are paralleled with the positive feedback structures. A high output voltage swing and a high DC gain are achieved by adding an adaptively biased common-source amplifier as the output stage leading to a class-AB operation. A large signal analysis, in weak inversion, is also done to mathematically describe both small- and large-signal characteristics. The proposed circuit was fabricated using TSMC $0.18 \mu \text{m}$ CMOS technology occupying a silicon area of $113\,\,\mu \text{m}\,\,\times 70\,\,\mu \text{m}$. Experimental results at a supply voltage of 0.4 V show a gain bandwidth of 7 kHz, a DC gain of 60 dB, and a slew rate of 79 V/ms with just 24 nW power dissipation while driving a capacitive load of $2\times 15$ pF. [ABSTRACT FROM AUTHOR]

Specialized hardware accelerators beyond von-Neumann, that offer processing capability in where the data resides without moving it, become inevitable in data-centric computing. Emerging non-volatile memories, like Ferroelectric Field-Effect Transistor (FeFET), are able to build compact Logic-in-Memory (LiM). In this work, we investigate the probability of error (Perror) in FeFET-based XNOR LiM, demonstrating the new trade-off between the speed and reliability. Using our reliability model, we present how Binarized Neural Networks (BNNs) can be proactively trained in the presence of XNOR-induced errors towards obtaining robust BNNs at the design time. Furthermore, leveraging the trade-off between Perror and speed, we present a run-time adaptation technique, that selectively trades-off Perror and XNOR speed for every BNN layer. Our results demonstrate that when a small loss (e.g., 1%) in inference accuracy could be accepted, our design-time and run-time techniques provide error-resilient BNNs that exhibit 75% and 50% (FashionMNIST) and 38% and 24% (CIFAR10) XNOR speedups, respectively. [ABSTRACT FROM AUTHOR]

We demonstrate SONOS (silicon-oxide-nitride-oxide-silicon) analog memory arrays that are optimized for neural network inference. The devices are fabricated in a 40nm process and operated in the subthreshold regime for in-memory matrix multiplication. Subthreshold operation enables low conductances to be implemented with low error, which matches the typical weight distribution of neural networks, which is heavily skewed toward near-zero values. This leads to high accuracy in the presence of programming errors and process variations. We simulate the end-to-end neural network inference accuracy, accounting for the measured programming error, read noise, and retention loss in a fabricated SONOS array. Evaluated on the ImageNet dataset using ResNet50, the accuracy using a SONOS system is within 2.16% of floating-point accuracy without any retraining. The unique error properties and high On/Off ratio of the SONOS device allow scaling to large arrays without bit slicing, and enable an inference architecture that achieves 20 TOPS/W on ResNet50, a $> 10\times $ gain in energy efficiency over state-of-the-art digital and analog inference accelerators. [ABSTRACT FROM AUTHOR]

This article presents a wide-band suppression technique of flicker phase noise (PN) by means of a gate–drain phase shift in a transformer-based complementary oscillator. We identify that after naturally canceling its second-harmonic voltage by the complementary operation itself, third-harmonic current entering the capacitive path is now the main cause of asymmetry in the rising and falling edges, leading to the $1/f$ noise upconversion. A complete $1/f^{3}$ PN analysis for the transformer-based complementary oscillator is discussed. By tuning gate–drain capacitance ratio, a specific phase-shift range is introduced at the gate and drain nodes of the cross-coupled pair to mitigate the detrimental effects of ill-behaved third-harmonic voltage, thus lowering the flicker PN. To further reduce the area and improve the PN in the thermal region, we introduce a new triple-8-shaped transformer. Fabricated in 22-nm FDSOI, the prototype occupies a compact area of 0.01mm2 and achieves $1/f^{3}$ PN corner of 70kHz, PN of −110dBc/Hz at 1MHz offset, figure-of-merit (FoM) of −182dB at 9GHz, and 39% tuning range (TR). It results in the best FoM with normalized TR and area (FoMTA) of −214dB at 1MHz offset. [ABSTRACT FROM AUTHOR]

In-memory computing using emerging technologies such as resistive random-access memory (ReRAM) addresses the ‘von Neumann bottleneck’ and strengthens the present research impetus to overcome the memory wall. While many methods have been recently proposed to implement Boolean logic in memory, the latency of arithmetic circuits (adders and consequently multipliers) implemented as a sequence of such Boolean operations increases greatly with bit-width. Existing in-memory multipliers require $O(n^{2})$ cycles which is inefficient both in terms of latency and energy. In this work, we tackle this exorbitant latency by adopting Wallace Tree multiplier architecture and optimizing the addition operation in each phase of the Wallace Tree. Majority logic primitive was used for addition since it is better than NAND/NOR/IMPLY primitives. Furthermore, high degree of gate-level parallelism is employed at the array level by executing multiple majority gates in the columns of the array. In this manner, an in-memory multiplier of $O(n.log(n))$ latency is achieved which outperforms all reported in-memory multipliers. Furthermore, the proposed multiplier can be implemented in a regular transistor-accessed memory array without any major modifications to its peripheral circuitry and is also energy-efficient. [ABSTRACT FROM AUTHOR]

Most analog circuits need a current reference generator to provide a stable biasing point for the transistors. Given the limited voltage headroom in advanced node technologies, there would be notable restrictions on the tolerance of the reference current deviation. Use of off-chip reference generators adds to the size of the system while the on-chip reference current generators are still partially dependent on the on-chip resistor values which is prone to technology variations. We propose an on-chip reference generator with a fully off-chip resistor which has less sensitivity to process variations. Monte-Carlo simulation results shows that the proposed has 31% more precision compared to the conventional on-chip reference generator. Measurement results in $0.18~{{\mu }}\text{m}$ CMOS shows that the chip produces a stable reference current that is defined based on an off-chip resistor. The proposed structure consumes the same current as conventional and does not add to the power consumption. [ABSTRACT FROM AUTHOR]

A capacitor-less (CL) low-dropout (LDO) regulator suitable to be incorporated in an on-chip system with low-voltage micro-energy-harvested supply, is proposed in this contribution. The differential input stage of the error amplifier includes bulk-driven MOS transistors, thus providing the LDO with an output voltage range that extends from the negative rail up to a level very close to the input voltage without the need of using a resistive feedback network. The circuit parameters relying on the feedback factor, $\beta $ , are maximized thanks to the use of a unitary value for this parameter. The CL-LDO has been designed and fabricated in standard 180-nm CMOS technology and optimized to operate with an input voltage equal to 0.6 V and a reference level of 0.5 V. The experimental characterization of the fabricated prototypes shows that, under these operating conditions, the LDO is able to deliver a load current above 0.75 mA with a total quiescent current of only 7.0 nA. Furthermore, the proposed voltage regulator is able to operate from input voltages as low as 0.4 V, delivering in this case a maximum load current of 30 $\mu \text{A}$. [ABSTRACT FROM AUTHOR]

There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today’s classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm. [ABSTRACT FROM AUTHOR]

A united-reference fractional counter (URFC) is proposed for multi-level time-to-digital converters (TDCs) used in direct time-of-flight (dToF) light detection and ranging (LiDAR) applications. The URFC combines the integer counter and the second-level interpolation in one functional block that derives both the integer part and the fractional part from the same synchronization result. Thus the proposed TDC has a more robust structure to deal with misalignment errors, and measurement results from different levels can be perfectly matched. High linearity and high precision can be guaranteed because of the united reference without calibration. The response time of the URFC decreases to hundreds of picoseconds, which makes it suitable for all output pulses from the avalanche photodiode. A TDC with the proposed URFC was implemented in 65nm standard CMOS technology with a detection range of $2.5~\mu \text{s}$ ($\sim 375\text{m}$) and a single shot precision of 27.63ps (~4.0mm). The power consumption is 51.4mW with a reference clock at 200MHz and a repetition rate at 999kHz. The INL and DNL are ±2.751 LSB and ±1.679 LSB, respectively. [ABSTRACT FROM AUTHOR]

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems. [ABSTRACT FROM AUTHOR]

We illustrate novel optimization techniques via simulations for Hopfield networks constructed from manufacturable three-terminal Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) synaptic circuit elements. We first present a computationally-light, memristor-based, highly accurate static compact model for the SONOS synapses used in our simulations. We then show how to exploit analog errors in programming resistances and current leakage, and the continuous tunability of the SONOS synapses to enable transient chaotic group dynamics, to accelerate the convergence of a Hopfield network. We project improvements in energy consumption and time to solution relative to existing CPUs and GPUs by at least 4 orders of magnitude, and also exceed the projected performance of two-terminal memristor-based crossbars in addition to a 100-fold increase in error-resilient array size (i.e. problem size). [ABSTRACT FROM AUTHOR]

To tackle the complexity of state-of-the-art electronic systems, silicon foundries continuously shrink the technology nodes and electronic design automation (EDA) vendors offer hierarchical design flows to decompose systems into smaller blocks. However, such a staged design methodology consists of various levels of abstraction, where margins will be accumulated and result in degradation of the overall design quality. This limits the full use of capabilities of both the process technology and EDA tools. In this work, a study of drive granularity of standard cells is performed and an interpolation method is proposed for drive option expansion within original cell libraries. These aim to investigate how industrial synthesis tools deal with the drive strength selection using different granularity sets. In addition, a fully-automated, multi-objective (MO) EDA digital flow is introduced for power, performance, area (PPA) optimisation based on drive strength refinement. This population-based search method better handles the increased difficulty of cell selection when using larger logic libraries, producing better optimised solutions than standard tool flow in this case. The achieved experimental results demonstrate how the improved drive granularity cells overall enhance the quality of designs and how a significant improvement in trading off PPA is achieved by the MOEDA flow. [ABSTRACT FROM AUTHOR]

Transistor aging phenomena manifest themselves as degradations in the main electrical characteristics of transistors. Over time, they result in a significant increase of cell propagation delay, leading to errors due to timing violations, since the operating frequency becomes unsustainable as the circuit ages. Conventional techniques employ timing guardbands to mitigate aging-induced delay increase, which leads to considerable performance losses from the beginning of the circuit’s lifetime. Leveraging the inherent error resilience of a vast number of application domains, approximate computing was recently introduced as an aging mitigation mechanism. In this work, we present the first automated framework for generating aging-aware approximate circuits. Our framework, by applying directed gate-level netlist approximation, induces a small functional error and recovers the delay degradation due to aging. As a result, our optimized circuits eliminate aging-induced timing errors. Experimental evaluation over a variety of arithmetic circuits and image processing benchmarks demonstrates that for an average error of merely $5\times 10^{-3}$ , our framework completely eliminates aging-induced timing guardbands. Compared to the respective baseline circuits without timing guardbands (i.e., iso-performance evaluation), the error of the circuits generated by our framework is $1208\times $ smaller. [ABSTRACT FROM AUTHOR]

This article presents a highly-efficient radio frequency energy harvester that utilizes an extra matching network to produce a passively-amplified adaptive compensation voltage. The compensation voltage produced on the gate of the transistors reduces the transistors’ conduction loss by increasing the gate-source voltage when transistors are on and reduces the leakage current by producing a negative gate-source voltage when the transistors are off. This is the first work that produces an adaptive compensation voltage without using active components, resulting in a significantly higher conversion efficiency if passive components of high quality are utilized. The mathematical derivations show that the forward conduction loss and the leakage current of the transistors are minimized by utilizing the proposed technique, increasing the overall efficiency. The proposed rectifier is fabricated in a TSMC 130 nm standard CMOS process, and measurement results and simulation results are in good agreement. Measurement results show that the rectifier achieves the maximum efficiency of 61% and 63.4% for battery load of 1.2 V and 1.5 V, respectively, which is at least 20 % larger than the efficiency of the conventional Dickson’s rectifiers. [ABSTRACT FROM AUTHOR]

For the first time, we demonstrate an optimization technique to synthesize circuits in the Negative Capacitance FET (NCFET) technology. NCFET is a rapidly emerging technology to replace the currently employed CMOS technology due to its profound ability to overcome the fundamental limit in scaling along with its full compatibility with the existing fabrication process. This is achieved by replacing the traditional transistor gate dielectric with a ferroelectric layer that manifests itself as a Negative Capacitance (NC), which magnifies the electric field. As a result, NCFET-based circuits can operate at a higher clock frequency without the need to increase the operating voltage. NC breaks one of the fundamental laws in physics in which the total capacitance of two capacitors connected in series becomes larger–instead of smaller in ordinary capacitors– than each of them. This could lead to sub-optimal netlists, suffering from significant increase in dynamic power and IR-drops. To suppress that, we employ the relation between delay decrease and capacitance increase of gates w.r.t ferroelectric thickness. Our technique takes an optimized netlist, obtained from commercial EDA tools, and then selectively determines the optimal ferroelectric thickness for each gate in the netlist, so that the maximum performance provided by NCFET is still achieved while the dynamic power is considerably decreased (45% on average), i.e., no trade-offs. Particularly, our technique enables the full exploitation of the performance benefits originating by NCFET, at a significantly lower (power) cost. Compared to state of the art, our technique decreases the energy-delay-product of circuits by 25% on average and reduces the deleterious effects of IR-drop by 56%. Hence, efficiency and reliability of circuits are improved without any loss in the obtained performance from NCFET. [ABSTRACT FROM AUTHOR]

In reality, individuals will spread their opinions by word of mouth, meanwhile sharing their opinions on social platforms. To gain a clear insight into this kind of behavior, we propose a diffusion model of various opinions in a two-layer interconnected network using some statistical characteristics of network structures. Theoretical analysis reveals that the final fraction of any opinion in one layer will get identical to that of the same opinion in the other layer. In particular, when the seed fraction of an opinion in one layer is different from that in the other layer, the diffusion behavior and final prevalence of opinions not only rely on the seed fractions of opinions, but also depend on the attributes of individuals that are active on different layers, including their inter-layer linking patterns and linking number. Further analysis shows that mass media will promote the spread of the opinion that is in accordance with its own. Finally, we illustrate the effectiveness of analytical results by simulating the spread of two opinions under four inter-layer linking patterns on three types of two-layer interconnected networks. The findings throw new light on some interesting phenomena in society, and facilitate decision-makers to orientate the prevalence of a special product. [ABSTRACT FROM AUTHOR]

Recurrent Neural Networks (RNNs) have been widely used in many sequential applications, such as machine translation, speech recognition and sentiment analysis. Long Term Short Term Memory (LSTM) and Gated Recurrent Unit (GRU) are widely used variants of RNN due to their effectiveness in overcoming gradient vanishing and exploding problems; however, compared to conventional RNN, their massive storage and computation requirements hinder their application. In addition, the recurrent structure of RNNs makes them prone to accumulate errors, resulting in a severe loss of accuracy. In this work, we propose a hybrid-iterative compression (HIC) algorithm for LSTM/GRU. By exploiting the error sensitivity of RNN, the gating units are divided into error-sensitive and error-insensitive groups, that are compressed using different algorithms. By using this approach, a 37.1 ×/32.3 × compression ratio is achieved with negligible accuracy loss for LSTM/GRU. Further, an energy efficient accelerator for bidirectional RNNs is proposed. In this accelerator, the data flow of the matrix operation unit based on the block structure matrix (MOU-S) is improved through rearranging weights; the utilization of BRAM is improved through a fine-grained parallelism configuration of matrix-vector multiplications (MVMs). Meanwhile, the timing matching strategy alleviates the load-imbalance problem between MOU-S and the matrix operation unit based on top-k pruning (MOU-P). When running at 200MHz on Xilinx ADM-PCIE-7V3 FPGA, the proposed design achieves an improvement in energy efficiency in a range of 5%-237% for LSTM networks, and an improvement of 58% for GRU networks compared with state-of-the-art designs. [ABSTRACT FROM AUTHOR]