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This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a 3 × 3 kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the 3 × 3 kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., G H and G V , respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient (G) of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing G H and G V cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window. [ABSTRACT FROM AUTHOR]

Brain-inspired flexible neuromorphic devices are of great significance for next-generation high-efficiency wearable sensing and computing systems. In this paper, we propose a flexible organic electrochemical transistor using poly[(bithiophene)-alternate-(2,5-di(2-octyldodecyl)- 3,6-di(thienyl)-pyrrolyl pyrrolidone)] (DPPT-TT) as the organic semiconductor and poly(methyl methacrylate) (PMMA)/LiClO4 solid-state electrolyte as the gate dielectric layer. Under gate voltage modulation, an electric double layer (EDL) forms between the dielectric layer and the channel, allowing the device to operate at low voltages. Furthermore, by leveraging the double layer effect and electrochemical doping within the device, we successfully mimic various synaptic behaviors, including excitatory post-synaptic currents (EPSC), paired-pulse facilitation (PPF), high-pass filtering characteristics, transitions from short-term plasticity (STP) to long-term plasticity (LTP), and demonstrate its image recognition and storage capabilities in a 3 × 3 array. Importantly, the device's electrical performance remains stable even after bending, achieving ultra-low-power consumption of 2.08 fJ per synaptic event at −0.001 V. This research may contribute to the development of ultra-low-power neuromorphic computing, biomimetic robotics, and artificial intelligence. [ABSTRACT FROM AUTHOR]

Bluetooth Low Energy Mesh (BLE Mesh) enables Bluetooth flexibility and coverage by introducing Low-Power Nodes (LPNs) and enhanced networking protocol. It is also a commonly used communication method in sensor networks. In BLE Mesh, LPNs are periodically woken to exchange messages in a stop-and-wait way, where the tradeoff between energy and efficiency is a hard problem. Related works have reduced the energy consumption of LPNs mainly in the direction of changing the bearer layer, improving time synchronization and broadcast channel utilization. These algorithms improve communication efficiency; however, they cause energy loss, especially for the LPNs. In this paper, we propose a constrained flooding algorithm based on time series prediction and lightweight GBN (Go-Back-N). On the one hand, the wake-up cycle of the LPNs is determined by the time series prediction of the surrounding load. On the other, LPNs exchange messages through lightweight GBN, which improves the window and ACK mechanisms. Simulation results validate the effectiveness of the Time series Prediction and LlightWeight GBN (TP-LW) algorithm in energy consumption and throughput. Compared with the original algorithm of BLE Mesh, when fewer packets are transmitted, the throughput is increased by 214.71%, and the energy consumption is reduced by 65.14%. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for a 1-bit full adder is proposed based on dynamic logic methodology, which utilises pass transistors. The clocking operation falls into two phases. The clocking operation consists of a pre-discharged cycle, during which pseudo capacitors are reset to zero when the clock signal is high, and an evaluation cycle, during which the circuit outputs the adder function when the clock signal is low. The circuit uses a combination of 12 pass-transistors to better implement the full adder logic function with the maximum of a NMOS threshold voltage drop. Moreover, the circuit has no direct connection to the power-supply node and so this can possibly save the power dissipation. Our new adder outperforms other 1-bit full adder structures in terms of power-delay factor, according to simulation results. [ABSTRACT FROM AUTHOR]

Summary This paper introduces an area‐effective and low‐power readout circuit structure tailored for high dynamic range (HDR) CMOS image sensors (CISs) utilizing dual conversion gain (DCG) imaging technology. A switched capacitor amplifier, which is applied at the comparator input port of the column‐parallel single‐slope analog‐to‐digital converter (SS ADC), is proposed to compensate for the charge injection and clock feed‐through introduced when the pixel switches between high conversion gain (HCG) and low conversion gain (LCG) modes. The proposed SS ADC is supplemented by the integration of a configurable counter, and the counter is specifically crafted for performing the A/D conversion of the readout voltage within a DCG pixel. Compared to the conventional DCG readout circuit, the proposed readout circuit use only one ADC for A/D conversion of HCG signals and LCG signals, which greatly reduces the area and power consumption of the readout circuit. Simulation results under 110 nm CMOS technology illustrate that the proposed 10‐bit SS ADC has a DNL of +0.78/−0.91 LSB and an INL of +1.91/−1.69 LSB, with a SNR of 57.2 dB and a SNDR of 55.95 dB, corresponding to an ENOB of 9 bits. The power consumption of the proposed SS ADC is 56.4 μW per column with a conversion time of 12 μs, and the simulation results show that the power consumption is 23.35% lower than the conventional structure and the area is saved by 24.69%. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) and blockchain are emerging technologies that have attracted attention in many industries, including healthcare, automotive, and supply chain. IoT networks and devices are typically low-powered and susceptible to cyber intrusions. However, blockchains hold considerable potential for securing low-power IoT networks. Blockchain networks provide security features such as encryption, decentralisation, time stamps, and ledger functions. The integration of blockchain and IoT technologies may address many of the security concerns. However, integrating blockchain with IoT raises several issues, including the security vulnerabilities and anomalies of blockchain-based IoT networks. In this paper, we report on our experiments using our blockchain test bed to demonstrate that blockchains on IoT platforms are vulnerable to DDoS attacks, which can also potentially lead to device hardware failures. We show that a number of anomalies are visible during either a DDoS attack or IoT device failure. In particular, the temperature of IoT hardware devices can exceed 90 °C during a DDoS attack, which could lead to hardware failure and potential fire hazards. We also found that the Block Transaction Rate (BTR) and network block loss percentage can increase due to corrupted hardware, with the BTR dropping to nearly zero blocks/sec and a block loss percentage of over 50 percent for all evaluated blockchains, and as high as 81.3 percent in one case. Our experiments demonstrate that anomalous temperature, latency, bandwidth, BTR, and network block loss percentage can potentially be used to identify DDoS attacks. [ABSTRACT FROM AUTHOR]

This paper presents a shock detection device for packages in the supply chain. The primary purpose is to identify package damage during storage, delivery, and handling. Additionally, products are likely to be damaged if dropped from a certain height, which sometimes does not appear on the package. By continuously measuring package vibrations and detecting shocks in the supply chain, consumers can gain an insight into the state of the product upon delivery. This paper presents the Smart Sticker implementation for ultra-low-power shock detection in the supply chain. The overall energy consumption must be kept as low as possible while continuously sensing the presence of shock to ensure that the Smart Sticker's battery lasts as long as possible. The Smart Sticker functions in three modes to meet the established constraints: low-power, active, and data transfer mode. While detecting the shock, the low-power mode uses the least amount of energy needed. If the shock exceeds the threshold, the Smart Sticker enters active mode, stores the detected g force value in memory, and then switches back to low-power mode. Finally, employing Near Field Communication (NFC) and energy harvesting, the data transfer mode allows the consumer to read the recorded data. The results show that the Smart Sticker for shock detection performs according to set requirements and successfully monitors and detects shock for packages in the supply chain. [ABSTRACT FROM AUTHOR]

This paper presents radiation hardened SRAM (namely LPDNUR and HSDNUR), both of which can self-recover from single-node and double-node upsets. LPDNUR uses a two-input C-element structure, which reduces the average power consumption because the stacked effect. Moreover, in order to reduce read access time (RAT) and write access time (WAT), the paper proposes HSDNUR, which uses a combination of NMOS and PMOS as the transistor for one-node data transmission, an approach that increases the current drive capability and reduces transmission delays. Compared to the state-of-the-art radiation-hardened SRAM design, such as QUCCE10T, QUCCE12T, We-Quatro, etc. The model results show that the average power consumption of LPDNUR is reduced by 24.59% on average, and the RAT and WAT of HSDNUR are reduced by an average of 35.71% and 24.14% respectively. • LPDNUR and HSDNUR fully achieve SNU and DNU recovery. • Average power of LPDNUR is 24.59% lower on average than other SRAM hardened since stack structure. • WAT and RAT of HSDNUR are 24.14% and 35.71% lower than other SRAM hardened on average by using TG. [ABSTRACT FROM AUTHOR]

Researchers are currently emphasizing the development of memory design based on memristors as a solution to the challenges posed by MOSFET-based designs. In this paper, a memristor-based ternary content addressable memory (MTCAM) has been designed and analyzed that is both high-speed and energy-efficient, while also occupying minimal area. The proposed MTCAM cell has five transistors and four memristors (referred to as 5T4M). It comprises two operational units: the main unit responsible for WRITE and SEARCH functions, composed of three transistors and two memristors, and the data recall unit, which is activated when data restoration is needed. This research work has been simulated in HSPICE with a 32-word array, each containing 144-digit MTCAM cells, using PTM 32 nm 0.9 V strained Si technology. The results indicate a search time of 204.6 ps and a search energy of 0.521 fJ/digit/search for worst-case mismatches, all achieved with a 1.2 V supply voltage. Furthermore, the implemented 32 × 144 MTCAM array provides a voltage margin of 331.38 mV. The 5T4M MTCAM design occupies an estimated area of 1.4904 μm2, which is notably compact compared to existing designs. [ABSTRACT FROM AUTHOR]

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power. [ABSTRACT FROM AUTHOR]

Purpose: Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell. Design/methodology/approach: Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles. Findings: Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts. Originality/value: The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell. [ABSTRACT FROM AUTHOR]

The survival rate for sudden cardiac arrest (SCA) is low, and patients with long-term risks of SCA are not adequately alerted. Understanding SCA's characteristics will be key to developing preventive strategies. Many lives could be saved if SCA's early onset could be detected or predicted. Monitoring heart signals continuously is essential for diagnosing sporadic cardiac dysfunction. An electrocardiogram (ECG) can be used to continuously monitor heart function without having to go to the hospital. A zeolite-based dry electrode can provide safe on-skin ECG acquisition while the subject is out-of-hospital and facilitate long-term monitoring. To the ECG signal, a low-power 1 μW read-out circuit was designed and implemented in our prior work. However, having long-term ECG monitoring outside the hospital, i.e., high battery life, and low power consumption while transmission and reception of ECG signal are crucial. This paper proposes a prototype with a 10-bit resolution ADC and nRF24L01 transceivers placed 5 m apart. The system uses the 2.4 GHz worldwide ISM frequency band with GFSK modulation to wirelessly transmit digitized ECG bits at 250 kbps data rate to a physician's computer (or similar) for continuous monitoring of ECG signals; the power consumption is only 11.2 mW and 4.62 mW during transmission and reception, respectively, with a low bit error rate of ≤0.1%. Additionally, a subject-wise cross-validated, three-fold, optimized convolutional neural network (CNN) model using the Physionet-SCA dataset was implemented on NVIDIA Jetson to identify the irregular heartbeats yielding an accuracy of 89% with a run time of 5.31 s. Normal beat classification has an F1 score of 0.94 and a ROC score of 0.886. Thus, this paper integrates the ECG acquisition and processing unit with low-power wireless transmission and CNN model to detect irregular heartbeats. [ABSTRACT FROM AUTHOR]

In this paper, the impact of the inductive peaking bandwidth enhancement technique on the input-referred noise performance of a 10 Gbps optical receiver, which includes the CMOS Regulated Cascode (RGC) Transimpedance Amplifier (TIA) is investigated and analyzed. By examining the noise equations in this paper, a novel low-noise design methodology, is introduced. Additionally, through the implementation of the structured gm/ID\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$${\text{g}}_{\text{m}}/{\text{I}}_{\text{D}}$$\end{document} approach and by selecting the suitable transistor dimensions, the power consumption as well as the noise values are reduced, while the values of the obtained gain and bandwidth are increased. To verify the performance of the designed TIA, the circuit issimulated in HSPICE using 90 nm CMOS technology parameters. The simulation results show the obtained gain value of 55.45 dBΩ, a bandwidth of 7.51 GHz and an input referenced noise value of 15.7 pA/√Hz at the 1.2 V power supply, while the circuit consumes 0.75 mW of power. [ABSTRACT FROM AUTHOR]

Wireless Body Area Network (WBAN) is a wireless network of short-range communication protocols for remote healthcare monitoring with the possibility of giving freedom of human body movements. Sensor nodes (motes) are usually located under the skin, implanted deep in the body, or ingested, as in the rare case of smart pills for medical and non-medical usage. Since the necessary connections of wearable and implantable devices are wireless, and the components use low batteries, processing and transferring the critical data can deplete the nodes' power. In most cases, it is impossible to exchange or re-power batteries. Holter monitoring, loop recorders, and wireless capsule endoscopy are some of the WBAN's applications for saving and transferring medical data. Wireless capsule endoscopy is the application for image transmission in WBANs, and the image compression in common is a specific segment of capsule endoscopy. Since the better compression of images increases the frame rate and typically improves the diagnosis process, selecting the compression algorithm should be relevant. The considerable scope of this comprehensive study pays attention to the various biomedical data compression approaches in WBANs. This paper focuses on power-efficient schemes of remote healthcare networks. In this survey article, the energy-based biomedical data compression approaches of WBANs and remote healthcare networks are accurately classified based on lossy, lossless, and hybrid techniques; later, a comprehensive comparison of each specific method's power consumption is presented. [ABSTRACT FROM AUTHOR]

The constant growth of social media, unconventional web technologies, mobile applications, and Internet of Things (IoT) devices create challenges for cloud data systems in order to support huge datasets and very high request rates. NoSQL databases, such as Cassandra and HBase, and relational SQL databases with replication, such as Citus/PostgreSQL, have been used to increase horizontal scalability and high availability of data store systems. In this paper, we evaluated three distributed databases on a low-power low-cost cluster of commodity Single-Board Computers (SBC): relational Citus/PostgreSQL and NoSQL databases Cassandra and HBase. The cluster has 15 Raspberry Pi 3 nodes with Docker Swarm orchestration tool for service deployment and ingress load balancing over SBCs. We believe that a low-cost SBC cluster can support cloud serving goals such as scale-out, elasticity, and high availability. Experimental results clearly demonstrated that there is a trade-off between performance and replication, which provides availability and partition tolerance. Besides, both properties are essential in the context of distributed systems with low-power boards. Cassandra attained better results with its consistency levels specified by the client. Both Citus and HBase enable consistency but it penalizes performance as the number of replicas increases. [ABSTRACT FROM AUTHOR]

With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (−28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of −76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7. [ABSTRACT FROM AUTHOR]

This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T) SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based cross-coupled inverters comprise the storage cell of the proposed MST11T bit cell. In comparison with conventional inverters, ST-based inverters have sharp voltage transfer characteristics. As a result, the proposed bit cell's stability performance increases. The proposed SRAM cell's leakage power consumption is reduced because of the use of stacked N-type transistors. For the read operation of the proposed bit cell, the read decoupled technique is used. As a result, the read static noise margin (RSNM) has greatly improved. The proposed bit cell's write static noise margin (WSNM) is increased by adopting feedback-cutting methodology. The performance of the proposed bit cell is compared with that of conventional 6 T, conventional 8 T, Schmitt-trigger 10 T (known as ST2), modified PMOS-PMOS-NMOS-based cell core 10 T (MPPN10T), feedback-cutting 11 T (FC11T), Schmitt-trigger 11 T (ST11), and Schmitt-trigger 12 T (ST12T) cells. According to the simulation results, the proposed MST11T SRAM cell has RSNM of 2.42, 1.18, 1.71, 1.30, and 1.80 times higher when compared to 6 T, FC11T, ST2, MPPN10T, and ST12T, respectively. The WSNM of the proposed bit cell has been increased by 1.56, 2.44, 1.28, 1.71, 1.35, 1.52, and 1.02 times, respectively, over 6 T, 8 T, ST2, MPPN10T, FC11T, ST11T, and ST12T. Furthermore, the suggested cell has a read delay that is 1.32, 1.79, and 1.53 times lower than ST11T, FC11T, and ST12T, respectively. The proposed bit cell has a write delay that is 1.14 and 1.63 times lower than FC11T and ST11T, respectively. The proposed MST11T bit-cell consumes 3.74, 1.56, 4.59, 5.38, and 4.83 times less leakage power than the 8 T, ST2, MPPN10T, FC11T, and ST12 bit-cells, respectively. When compared to 8 T/ST2/MPPN10T/ST12T at 0.2 V supply voltage, the enhanced facts incur a 4.87/3.79/3.78/1.97 penalty in write delay. The figure of merit (FOM) is derived as a result of this extensive access to the revolutionary SRAM cell performance, i.e., offering greater values at a 0.2 V DC supply voltage. In addition, the paper examines the impact of manufacturing process and temperature changes on MST11T cell enactment, as well as the circuit robustness using HSPICE with 7-nm FinFET technology. [ABSTRACT FROM AUTHOR]

Variable energy constraints affect the implementations of neural networks on battery-operated embedded systems. This paper describes a learning algorithm for randomization-based neural networks with hard-limit activation functions. The approach adopts a novel cost function that balances accuracy and network complexity during training. From an energy-specific perspective, the new learning strategy allows to adjust, dynamically and in real time, the number of operations during the network's forward phase. The proposed learning scheme leads to efficient predictors supported by digital architectures. The resulting digital architecture can switch to approximate computing at run time, in compliance with the available energy budget. Experiments on 10 real-world prediction testbeds confirmed the effectiveness of the learning scheme. Additional tests on limited-resource devices supported the implementation efficiency of the overall design approach. [ABSTRACT FROM AUTHOR]

Achieving high-gain and low-noise operation of bulk-driven (BD) operational transconductance amplifier (OTA) with low-power consumption is a challenging task owing to inherent low transconductance and high noise in BD MOSFET. In this paper, we report a self-cascode partial positive feedback (SCPPF) approach-based BD OTA and have fairly compared the results with regular single MOS partial positive feedback (PPF) approach-based BD OTA. In comparison to regular BD PPF OTA, the proposed BD SCPPF OTA yields an improved gain of 68.71 dB, gain-bandwidth of 39.4 kHz, power consumption of 630 nW, output impedance of 0.4 MΩ and common mode rejection ratio of 134.4 dB for same input referred noise of 1.11 μV/√ Hz at frequency of 10 Hz and supply voltage of ±0.5 V. The area consumed by BD SCPPF OTA is 0.0523 mm2. The proposed BD SCPPF OTA can be possibly used to improve the performance of biomedical analog front-end sensing and signal processing systems. [ABSTRACT FROM AUTHOR]

This paper presents a sub-microwatt sub-bandgap voltage and current reference that can generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents concurrently. The voltage reference is derived from the process-insensitive silicon bandgap voltage of a bipolar junction transistor, whereas the current reference is made by combining PTAT and CTAT currents. Line regulation is improved by incorporating cascode devices without an operational amplifier (opamp). Fabricated in a standard 0.18-µm CMOS process, the proposed bandgap reference occupies an active area of 0.4 mm2. The current and voltage reference ( I REF and V REF ) are measured as 170 mV and 21 nA, respectively, while the start-up settling response is measured as 20 ms at room temperature. The average temperature coefficient of I REF and V REF is 79.8 ppm/°C and 87.93 ppm/°C across the temperature range from − 40 to 120 °C, respectively. The power consumption is 134 nW at the minimum supply voltage of 1.2 V. The power supply ripple rejection of V REF is measured as − 10 dB at 100 kHz without any filtering capacitor, when the 1.6 V input line voltage is distorted by a 300-mVp-p ripple. The measured line sensitivity of the voltage and current reference is 0.142%/V and 0.757%/V, respectively. [ABSTRACT FROM AUTHOR]

Content addressable memory (CAM) is a hardware search engine (HSE) used for accelerating lookup functions in tagged cache, translation lookaside buffers (TLBs) and network routers. Despite its speedy search feature, augmentation of compare-evaluate blocks to storage units costs additional area. Activation of cells and matchlines (MLs) during search operations is responsible for huge dynamic-power dissipation. This paper proposes a shared ML scheme (SMS) based on a two-step evaluation CAM cell, in order to reduce ML transitions per word besides improving density in the comparison units. A 64 × 32-bit proposed SMS-CAM, using 45-nm CMOS technology, dissipates 1.06 fJ/bit/search and achieves 100.77-ps search time. At the cost of 6.55% sacrificial delay over a conventional CAM, the proposed CAM reduces 12.38% – 30.48% energy over a self-power off gating, the conventional and an early terminate ML precharge designs. Low energy-delay results better trade-off budget besides decreasing macro area in the SMS-CAM, which could be useful in search applications of network devices. • A 2-bit storage with common evaluation (2B-CE) involving two-step comparison • Two side-by-side CAM cells (one 2B-CE based cell) share one matchline (ML) node • Shared matchline scheme limits ML discharge to only 1 path per 2-bit mismatches • Lesser ML discharge paths with shared matchline scheme (SMS) saves dynamic power • N/2 proposed 2B-CE cells are designed in NOR-type ML to form an N-bit CAM word • SMS-CAM sustains high-speed searches owing to the parallel cells in NOR-type ML • Comparison of SMS-CAM with referred CAMs verifies performance and reliability [ABSTRACT FROM AUTHOR]

This paper presents the first implementation of a spiking neural network (SNN) for the extraction of cepstral coefficients in structural health monitoring (SHM) applications and demonstrates the possibilities of neuromorphic computing in this field. In this regard, we show that spiking neural networks can be effectively used to extract cepstral coefficients as features of vibration signals of structures in their operational conditions. We demonstrate that the neural cepstral coefficients extracted by the network can be successfully used for anomaly detection. To address the power efficiency of sensor nodes, related to both processing and transmission, affecting the applicability of the proposed approach, we implement the algorithm on specialised neuromorphic hardware (Intel ® Loihi architecture) and benchmark the results using numerical and experimental data of degradation in the form of stiffness change of a single degree of freedom system excited by Gaussian white noise. The work is expected to open a new direction of SHM applications towards non-Von Neumann computing through a neuromorphic approach. [ABSTRACT FROM AUTHOR]

Static random-access memories (SRAMs), which are the most ubiquitous in modern system-on-chips, suffer from high power dissipation and poor stability in advanced complementary metal–oxide–semiconductor (CMOS) technology due to continuous learning, which leads to increased short-channel effects (SCEs), thereby, leading to use of new nano-devices. The fin-shaped field-effect transistor (FinFET) with lots of impressive attributes like mitigated SCEs is an efficient replacement for CMOS to overcome the aforementioned concerns. In this regard, this paper aims to explore a novel single-bitline 9-transistor (SB9T) SRAM with bit-interleaving capability appropriate for low-power near-threshold operation in 7-nm FinFET technology. The relative performance of the proposed SB9T is estimated by comparing it with other seven contemporary SRAMs such as conventional 6 T, write–read enhanced 8T (WRE8T), transmission gate read decoupled 9T (TGRD9T), one-sided Schmitt-trigger 9T (ST9T), data-independent read port 10T (DIRP10T), PMOS-PMOS-NMOS-based cell core 10T (PPN10T), and feedback-cutting 11 T (FC11T) at a near-threshold supply voltage of 0.5 V. Simulation results inferred that the SB9T offers 1.77 × /1.36 × and 2.35 × /13.13 × /1.30 × improvement in read stability and writability compared to WRE8T/ST9T and 6 T/DIRP10T/PPN10T, respectively. Furthermore, it consumes the best dynamic read power, which is at least 1.50 × , the third-best dynamic write power, and the second-best static power. The proposed SB9T SRAM offers 2.89 × /2.37 × improvement in dynamic write power/static power, at the expense of 1.742 × area overhead, compared to 6 T. [ABSTRACT FROM AUTHOR]

This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor. This improves hold stability and leakage power dissipation. The read and write operations of the proposed cell are performed with the aid of separated paths and bitlines, lowering power consumption. The strong cell core and decoupled read path eliminate the read-disturbance issue in the proposed cell, resulting in read static noise margin (RSNM) enhancement. Furthermore, the feedback-cutting write-assist technique used in the proposed design mitigates the writing '1' issue; consequently, write static noise margin (WSNM)/write margin (WM) improves. To prove the superiority of the proposed SRAM cell in various performance metrics, it is compared with state-of-the-art SRAM cells, introduced as 6T, TG9T, 10T-P1, and SB11T, using HSPICE and 16-nm CMOS technology node taking into consideration the impact of the severe process, voltage, and temperature (PVT) variations. Obtained results at VDD = 0.7 V show that the proposed design offers the highest HSNM/RSNM/WSNM (or WM). The read/write delay of the proposed cell is 3.92X/2.37X higher than that of the 6T SRAM cell due to its single-ended reading/writing structure. However, in terms of power consumption, the proposed cell exhibits 1.64X/1.54X lower than that of 6T SRAM cell. Though the proposed cell occupies a 1.24X higher area compared with the 6T SRAM cell due to its higher count of transistor, it shows the highest proposed figure of merit among all the studied SRAM cells, which is 26.90X higher than that of 6T SRAM cell. [ABSTRACT FROM AUTHOR]

This paper presents a robust low‐power 10T SRAM cell (RLP10T) with a novel read/write assist mechanism, improving both read static noise margin (RSNM) and write static noise margin (WSNM) simultaneously. To assess its relative strength, we compared the proposed cell with recently published SRAM cells such as WRE8T, 10T‐P1, HFBS10T, WALP11T, and SE11T in 16‐nm CMOS technology node. The RLP10T cell shows 3.55/1.07 times higher/lower RSNM compared to the WRE8T/WALP11T cell and offers at least 1.10 times higher WSNM. Due to the presence of three series‐connected transistors in its read path, which includes a strong pull‐down transistor, the proposed design shows 1.23 times shorter read delay (TRA) than that of 10T‐P1/HFBS10T cell. The proposed cell incurs a penalty of high write delay (TWA) due to its long write path. However, it exhibits the fourth (second)‐best read (write) power, attributed to its single‐ended structure and lower read (write) frequency. It also dissipates acceptable leakage power due to its single‐bitline structure and the presence of stacked transistors in its read path and pull‐down path of one of the inverters in the cell core. Subjected to the severe process, voltage, and temperature variations, the RLP10T cell offers at least 1.31/1.09/1.03 times lower variability in RSNM/WSNM/TRA at VDD = 0.7 V, at the cost of 1.22 times area overhead compared to the WRE8T cell. [ABSTRACT FROM AUTHOR]

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient CMOS image sensor (CIS) for always-on object detection by using 1-bit log-gradient feature extraction in analog current domain. Compared with traditional image sensors with high-resolution ADCs, the proposed CIS extracts gradients in ratio form and generates feature maps at 1-bit resolution, which eliminates unnecessary background information and illumination-related data, and reduces the data computation in the later detector. The system containing the proposed CIS and back-end ANN detector is modeled with python and the simulation achieves an accuracy of 93.2 % for person detection. The CIS employs current mode divider and comparator to compute the gradient ratios. An accurate and configurable muti-input and muti-output (MIMO) current divider is proposed, composed of two cascaded modified second generation current controlled conveyors (M-CCCIIs). The proposed CIS was fabricated in a 0.18 μm standard CMOS process and realized a frame rate of 170 fps and an energy efficiency of 337 pJ/pixel in a power consumption of 1.1 mW. Experimental results show that the proposed CIS can realize the function of extracting log-gradients. [ABSTRACT FROM AUTHOR]

In this paper, a new high-gain operational transconductance amplifier (OTA) circuit is designed. The proposed circuit uses bulk-driven technique to reduce the required supply voltage while gain-boosting as well as positive feedback techniques are used to increase the gain of the circuit and compensate the gain reduction effect due to the use of bulk-driven transistors. The performance of the proposed circuit is simulated using 180-nm CMOS technology parameters and is optimized using an optimization algorithm for the main purpose of minimizing the power consumption of the circuit. Simulated performance of the proposed circuit for 1.2 V DC supply voltage shows 94.8 dB gain, 203-MHz bandwidth, and slew-rate of 365-V/µS while occupying die area of 1360 µm2. However, the proposed circuit is also designed for a low-voltage scenario with 0.75 V DC supply voltage that results in 73.7 dB gain, 131-MHz bandwidth, and slew-rate of 149-V/µS. [ABSTRACT FROM AUTHOR]

Sensitivity is a key parameter for microspeakers, especially in low-power applications such as consumer electronics, medical devices and Internet of Things. However, the sensitivities of most reported piezoelectric MEMS speakers are inferior to those of commercially available electrodynamic speakers. Design of high-sensitivity piezoelectric MEMS speakers requires an analytical expression of sensitivity, which is not yet available. In this paper, the analytical expression is derived, and an ultrahigh-sensitivity piezoelectric MEMS speaker is designed, fabricated and characterized. The sensitivities of the speaker in an ear simulator are 107 dB/mW, 104 dB/mW and 105 dB/mW at 250 Hz, 1 kHz and 10 kHz, respectively, which are the highest among piezoelectric MEMS speakers. The analytical calculation results and measurement data are perfectly matched. Furthermore, the speaker is based on thin-film AlN instead of commonly used thin-film PZT. This work demonstrates that the ultrahigh-sensitivity piezoelectric AlN MEMS speaker consumes 10 times less power than a typical 6 mm electrodynamic speaker; and the developed analytical expressions provide valuable design insights into piezoelectric MEMS speakers for high sensitivity and low power. [2022-0063] [ABSTRACT FROM AUTHOR]

Purpose: Multipliers that form the basic building blocks in most of the error-resilient media processing applications are computationally intensive and power-hungry modules. Therefore, improving the multiplier's performance in terms of area, critical path delay and power has become an important research area. This paper aims to propose two improved multiplier designs based on a new approximate compressor circuit to reduce the hardware complexity at the partial product reduction stage. The proposed approximate 4:2 compressor design significantly reduces the overall hardware cost of the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure. Design/methodology/approach: The multiplier designs implemented using the proposed approximate 4:2 compressor are targeted for error-resilient applications. For fair comparisons, various multiplier designs, including the proposed one, are implemented in MATLAB. The quality analysis is carried out using standard images, and metrics such as structural similarity index are computed to quantify the result of proposed designs with the existing architectures. Next, Verilog gate-level designs are synthesized to compute area, delay and power to prove the efficacy of the proposed designs. Findings: Exhaustive error and hardware analysis have been carried out for the existing and proposed multiplier architectures. Error analysis carried out using MATLAB proves that the proposed designs achieve better quality metrics than existing designs. Hardware results show that area, the power consumed and critical path delay are reduced up to 39.8%, 51.7% and 15.9%, respectively, compared to the existing designs. Toward the end, the proposed designs impact is quantified and compared with existing designs on real-time image sharpening and image multiplication applications. Originality/value: The area, delay and power metrics of the multiplier can be improved using an approximate compressor in an error-resilient application. Accordingly, in this work, a new compressor is proposed that reduces the hardware complexity in the multiplier architecture. However, the proposed approximate compressor, while reducing the computational complexity, tends to introduce error in the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure. With the help of the approximate compressor and a technique of input realignment, hardware efficient and highly accurate multiplier designs are achieved. [ABSTRACT FROM AUTHOR]

This paper presents a new family of innovative operational transconductance amplifier (OTA) topologies based on CMOS inverter structures, with improved gain and energy-efficiency. This new family of OTA designs is suitable for biomedical and healthcare circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the state-of-the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltage-combiners specifically targeting low voltage applications, e.g., supplies below 1 V. The usage of voltage-combiners to bias the OTAs improves the gain and the gain-bandwidth product, therefore improving the energy-efficiency figure-of-merit. High values of figure-of-merit are achieved in both implementations, i.e., more than 1600 MHz × pF/mA and 2000 MHz × pF/mA, gain values above 53 dB and 50 dB under supply sources of 2 V and 0.7 V respectively. The folded voltage-combiners biased OTA is able to operate correctly under a voltage supply down to 0.7 V with proper DC biasing. The results are finally compared with state-of-the-art in this field and the potential of the circuits is fulfilled using a state-of-the-art layout-aware integrated-circuit optimization framework, AIDA, particularly relevant in order to overcome the device stacking problematic for lower voltages. [ABSTRACT FROM AUTHOR]

In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. • In dynamic comparators, the pre-amplifier amplifies the input differential signal to some extent then the latch finalizes the comparison. After some moment from the latch activation, the pre-amplifier is wasting power and sometimes reduces the gain worsening the power consumption and offset voltage. The aim of the proposed comparator is to overcome this issue. In low-offset comparators, the sizing of the input transistors of the pre-amplifier is chosen large for matching purposes so that the pre-amplifier consumes the dominant part of the total power consumption making it a good candidate to work on for low-power applications. In this paper, a low power method for dynamic comparators is presented using which the power consumption of the pre-amplifier is controlled in a proper way. Therefore, not only the power is saved but also the input referred offset voltage is improved. • In the paper, analytical derivations are presented to quantify the amount of power saving. Simulations showed the derivations are consistent with the circuit. The proposed method is able to reduce the power consumption by about 30%-40% and the offset voltage by about 20%. Post layout simulation of the RC-CC extracted circuit confirms the benefits of the proposed comparator. • The proposed method is applicable to different types of the double tail comparators. This method is simple yet effective in power reduction. [ABSTRACT FROM AUTHOR]

This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply voltage, achieves a noise floor of 2μV/⎷Hz within the frequency range from 1 Hz to 10 kHz. The current consumption of the CMOS photoreceptor is 541 nA. This paper shows the need for the design of phototransduction circuit at low voltage, low noise and how these constraints are reflected in the design of CMOS vision sensor. [ABSTRACT FROM AUTHOR]

This paper proposes a 4th-order class-AB low-pass filter (LPF) for wearable biological healthcare applications designed by cascading two 2nd-order LPFs. The proposed class-AB LPF uses quasi-floating gate (QFG), flipped source follower (FSF) and level-shifter (LS) techniques to boost its performance. The LPF is designed and validated in CMOS 180 nm technology which emulates the post-layout gain of −0.212 dB, bandwidth of 100 Hz, dynamic range (DR) of 50.26 dB, total harmonic distortion (THD) of −52.5 dB and figure of merit (FOM) of 1.71 × 10-15 J. The class-AB QFG FSF LPF consumes power and area of 0.224 nW and 0.0196 mm2, respectively. Furthermore, the statistically determined coefficient of variation for proposed LPF with 1000 iterations for gain is −0.035, THD is −0.172 and DR is 0.04, respectively. The class-AB QFG FSF LPF is compared with other LPFs which establishes its advantage in terms of low-power consumption and least figure of merit thus confirming its suitability for wearable healthcare applications. [ABSTRACT FROM AUTHOR]

This paper presents a 10 bits low-power direct digital IF to RF digital-to-analog (RF-DAC) fabricated in a 110 nm CMOS technology with a core area of 0.08 mm 2. The DAC uses sixteen current mode double balanced mixers designed without a tail transistor with different weights to convert IF output to RF output. The digital IF signal is modulated by a digital Σ − Δ modulator with 1-bit IF output. The RF-DAC with a bandwidth of 300 KHz consumes 17.3 mA from a 1.5 V supply. [ABSTRACT FROM AUTHOR]

In this paper, a new low-power full-adder circuit based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low-power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology. Using the proposed approach, the basic logic circuits such as XOR and XNOR gates are implemented which results in a full-swing, full-adder cell in the CNFET technology. The proposed circuit is simulated in HSPICE using CNFET model parameters. Finally, the simulation results justify a good improvement in the major circuit performances such as power consumption, delay and power-delay product (PDP) parameters for the proposed full-adder circuit. • A new Dynamic-GDI Low-Power Full-Adder circuit in CNFET technology is presented. • The design is based on the proper combination of Dynamic and GDI logic design techniques. • The proposed design not only significantly reduces the power consumption, but also reduces the PDP and layout area considerably. • The performance of the proposed circuit is simulated in HSPICE, using the STANFORD CNFET model parameters. [ABSTRACT FROM AUTHOR]

In this paper, a new hybrid low-power and area efficient Carry Look-Ahead Adder in CNFET technology based on the full-swing Gate Diffusion Input (GDI) technique is proposed. The proposed CLA design in GDI logic style, not only decreases the circuit area effectively but also decreases the power consumption and delay parameters as well. The proposed design is simulated in HSPICE using the CNFET model parameters. Finally, the simulation results justify a good improvement in the circuit performance parameters such as power consumption, delay, chip size area and power-delay product (PDP) for the proposed CLA circuit. [ABSTRACT FROM AUTHOR]

Most image processing applications are naturally imprecise and can tolerate computational error up to a specific limit. In such applications, savings in power are achieved by pruning the data path units, such as an adder module. Truncation, however, may lead to errors in computing, and therefore, it is always a challenge between the amount of error that can be tolerated in an application and savings achieved in area, power and delay. This paper proposes a segmented approximate adder to reduce the computation complexity in error-resilient image processing applications. The sub-carry generator aids in achieving a faster design while carry speculation method employed improves the accuracy. Synthesis results indicate a reduced die-area up to 36.6%, improvement in delay up to 62.9%, and reduction in power consumption up to 34.1% compared to similar work published previously. Finally, the proposed adder is evaluated by using image smoothing and sharpening techniques. Simulations carried out on these applications prove that the proposed adder obtains better peak signal-to-noise ratio than those available in the literature. [ABSTRACT FROM AUTHOR]

Distributed arithmetic (DA) is an efficient way to implement sum‐of‐product units, which can be used in applications such as FIR filters, filter banks, image processing, and convolutional neural networks in IoT hardware accelerators. In this paper, a low‐power architecture is offered centered on two key steps, coarse‐grain power‐performance partitioning and fine‐grain separated power supply, and tuned a level shifter in any digital systems implemented based on RTL design. To examine the new design approach, two methods are proposed, at first exploring the power consumption and critical delay path and then separating the power supply of datapath and controller in DA with/without utilizing an implicit level shifter. To investigate power consumption and timing parameters, two 5‐tap and 16‐tap FIR‐filters are implemented in 65‐nm CMOS standard technology. In proposed1, dynamic and static power consumption of 16‐tap (5‐tap) FIR‐filter is improved by 30% (15%) and 59% (59%), respectively. Nevertheless, the delay and slope of the generated signal in the shiftreg are significantly increased by reducing the power supply. To tackle this issue, the second method suggested with 26% (14%) improvement in dynamic power and 55% (58%) in static power consumption, which does not increase any delay in the output of shiftreg compared to conventional DA‐based FIR filter with solitary power supply. [ABSTRACT FROM AUTHOR]

With the emergence of the internet-of-things (IoT), many devices process data through the IEEE 802.11 wireless networks. To satisfy the increased data processing, the wireless fidelity (Wi-Fi) networks must have sufficient capacity. IEEE 802.11ax is formulated to provide higher data processing capabilities for IoT applications. The IEEE 802.11ax receiver operating at 5 GHz must be able to withstand interference from nearby IoT applications. Hence, the low-noise amplifier (LNA) employed in such receivers must have a high input-referred third-order intercept point (IIP3). This paper aims to present a wideband LNA operating at 5 GHz with high IIP3 for modern IoT transceivers using IEEE 802.11ax protocol. The LNA is designed and implemented in UMC 65 nm CMOS technology using the Cadence virtuoso design tool. The proposed LNA can provide a maximum gain of 17.64 dB while consuming 8.18 mW of power from a 1.2 V supply. It can be noted that the minimum noise figure (NF) achieved is 3.67 dB and the corresponding IIP3 is 9.44 dBm at 5 GHz from the pre-layout simulations. [ABSTRACT FROM AUTHOR]

In this paper, a low-power structure as an inverter-base circuit is reported for broadband applications. The focus in this study is in obtaining a low-power structure. By applying cascoded structure to an inverter as a feedforward network in the structure, the DC current and hence the power dissipation are decreased. Also, by adding a two-stage active feedback, which yields no miller capacitance, to the cascoded inverter, the structure of the TIA is completed. Simulation results in HSPICE using 90nm CMOS technology parameters show 41 dBΩ transimpedance gain, 6.5 GHz frequency bandwidth and 2.7 µArms input referred noise, which consumes only 1.67mw power at 1V supply. Results and analysis indicate that the proposed TIA is suitable to work as a low-power 10 Gbps transimpedance amplifier in an optical receiver. [ABSTRACT FROM AUTHOR]

Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data and respond quickly to requests. However, achieving low-power and stable SRAM cells, which are essential for IoT systems, is not possible with CMOS technology due to scaling issues. As a result, new nanoscale devices, such as FinFET, have been introduced as a potential replacement for CMOS in SRAM design. This paper presents a new FinFET-based 8 T SRAM cell with separate reading and writing paths. The cell uses read-decoupling and write-assist pull-down path cut techniques to improve read stability and writability, respectively. Single-ended reading and writing structures reduce power consumption, and stacking transistors, along with read bitline leakage elimination, reduces leakage power dissipation. The proposed cell's efficiency is evaluated using HSPICE simulator with 10-nm FinFET technology and is compared with conventional 6 T, single-bitline 7 T (SB7T), single-ended 8 T (SE8T), and transmission gate read-decoupled 9 T (TRD9T) SRAM cells at V DD = 0.35 V. The proposed cell improves read stability by 2.59×/1.04 × and enhances writability by 1.38×/1.01 × compared to 6 T/TRD9T and 6 T/SB7T, respectively. It also reduces read power by 28.25 %/19.60 % compared to the 6 T/SB7T and reduces write power by at most 33.40 % and at least 5.46 %. Moreover, the leakage power is reduced by at least 5.80 %. However, the proposed cell increases read/write delay by 1.77×/1.40 × and shows 1.23 × larger layout area compared to 6 T. [ABSTRACT FROM AUTHOR]