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Biased-Temperature-Instability (BTI) aging mechanism reduces Static-Noise-Margin (SNM) of SRAM cells. This leads to a higher Soft-Error-Rate (SER), lower reliability, and lower SRAMs’ stability in FPGAs. SNM partially improves by leveraging the recovery phase of BTI through flipping SRAM content. We propose STABLE, a three-step post-synthesis stress-aware technique, in order to reduce the impact of BTI-induced SNM reduction in FPGA Look-up-Tables (LUTs) using the SAT-based Boolean Matching (BM) algorithm. STABLE partitions Data-Flow-Graph (DFG) of the implemented design into different cones. First, the SAT-based BM algorithm finds a new configuration for each cone while their functionalities are preserved and all SRAMs are flipped. Second, cones that did not pass the first step can benefit from unused SRAMs in their partially-used LUTs for storing the flipped configurations of such LUTs. Finally, flipped configurations of fully-used LUTs are stored in the closest unused LUTs. The main configuration of the implemented FPGA design is swapped by the new flipped configuration, periodically. Our extensive experimental analysis demonstrates 69 and 70 percent on average improvements in the SNM reduction () and the SER increase ( $\Delta SER$), respectively. Since the proposed methodology is deployed after the FPGA placement and routing of the application, the overhead is negligible. [ABSTRACT FROM PUBLISHER]

Fault-tolerant minimal routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. Additionally, some non-faulty nodes that are helpless to make up of a fault-tolerant minimal path should also be routed around. How to label such non-faulty nodes efficiently is a major challenge. State-of-the-art solutions could not address it very well. We propose a path-counter method. It can label every node that are helpless to make up of a fault-tolerant minimal path with low time complexity. By counter the number of fault-tolerant minimal paths, it can: support arbitrary fault distribution, check the existence of fault-tolerant minimal paths, not sacrifice any available fault-tolerant minimal paths. [ABSTRACT FROM AUTHOR]

NoC technology is composed of packet-based interconnections, where the communication resources are distributed across the network. Therefore, the optimal resource utilization is a crucial consideration for efficient architectural designs. This paper studies the practicality of the Constraint Programming (CP) models for NoC architecture designs that effectively use a regular mesh with wormhole switching and the XY routing. The complexity of the CP models is compared with the earlier Mixed Integer Programming (MIP) models. Practical CP-based mapping and scheduling models are developed and results are reported on the benchmark datasets. Results indicate that mapping and scheduling problems can be solved at near optimality even under relatively shorter run-time limits as compared to those required by the MIP models. [ABSTRACT FROM AUTHOR]

This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior design alternative in terms of thermal constraints, power consumption as well as performance considerations. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage to minimize the overall communication cost among cores. We then solve the application scheduling problem to determine the optimum core types from a list of technological alternatives and to minimize the makespan. Moreover, an elegant CP model is proposed to solve VFI problem by mapping and grouping cores at the same time with scheduling the computation tasks as a limited capacity resource allocation model. The paper reports results based on real benchmark datasets from the literature. [ABSTRACT FROM AUTHOR]

Deep neural networks (DNNs) have been employed to different devices as a popular machine learning algorithm (ML) owing to deploy the Internet of Things (IoT), data mining in cloud computing, and web search engines, which MLs had an impressive effect on IoT's edge level nodes. Deploying DNN-based applications leads to memory access problems, including communication delay, energy efficiency, and bandwidth requirement. We propose a bus scheduling for data placement on distributed local buffers in a deep learning accelerator (DLA). The contributions of this paper include (1) providing a method for data-flow mapping between off-chip DRAM and distributed local buffers, and a flow mapping approach for data transfer between distributed local buffers and processing elements (PEs) (2) employing distributed local buffers in four directions for traffic distribution on a mesh based on memory access mechanism (3) bus scheduling for data placement on distributed local buffers. Simulated experiment based on typical DNN (i.e., AlexNet, VGG-16, and GoogLeNet) workflows demonstrates the effectiveness of the design: (1) the scheduling and mapping methods improve total runtime and bandwidth requirement by approximately 42.29% and 88.95% compared with TPU, respectively. Additionally, (2) our methods reduce total runtime for row-column stationary plus by approximately 99% compared with weight-stationary data-flow in CONV1 and CONV11 of VGG-16, respectively. This work reports the simulation results based on distributing AlexNet, VGG-16, and GoogLeNet's traffics as the popular CNNs and DNNs models, whereas it investigates our method's efficiency for other trained models. [ABSTRACT FROM AUTHOR]

Convolutional neural networks have been proposed as an approach for classifying data corresponding to a variety of datasets. Indeed, developments in data diversity and information technology have increased the complexity of deep learning algorithms. Numerous trained models have been proposed for supporting complex algorithms and data detachment with high accuracy. Convolutional operations increase when the convolution depth of neural networks increases. Thus, employing deep convolutional networks is challenging regarding energy consumption, bandwidth, memory requirements, and memory access. Different types of on-chip communication platforms and traffic distribution methods are effective in the improvement of memory access and energy consumption induced by data transfer. Also, dataflow mapping methods have an impressive effect on reducing or increasing delay and energy consumption caused by exchanging data between cores of a communication network. Different methods have been proposed to dataflow mapping on various networks for reducing total hop counts that led to improve performance and cost. Dataflow mapping approach can affect performance improvement of the inference phase in neural networks. This paper proposes various traffic patterns by considering different memory access mechanisms for traffic distribution of a trained AlexNet model on mesh topology. We propose a flow mapping method (FMM) on the mesh to determine the data flow efficiency of different traffic patterns on energy consumption. The FMM reduced energy and total flow by approximately 17.86% and 34.16%, respectively, using different traffic patterns. Thus, the FMM improved the performance of AlexNet traffic distribution while the impact on data flow reduced energy consumption. [ABSTRACT FROM AUTHOR]

While 3-D integrated circuits (ICs) offer many advantages over 2-D ICs, thermal management challenges remain unresolved. Thermal through-silicon-vias (TTSVs) are TSVs that facilitate heat transfer across stacked dies without carrying signal and provide a potential thermal management solution to 3-D ICs. However, the use of TTSVs increases the distance between IC blocks and signal delay. The trade-off between temperature and wirelength is difficult to avoid in TTSV-integrated 3-D ICs. Here, we present a hierarchical approach to optimize the floorplan of a 3-D Nehalem-based multicore processor via simulated annealing (SA). Our simulations show that an increase in the TTSV area accompanies a decrease in peak temperature but the wirelength strongly depends on the TTSV placement, which is uniquely optimized for each case of the allowed TTSV area. Compared to the floorplan with a fixed TTSV placement that places TTSV between cores, our algorithm optimally places TTSVs between IC blocks and finds an optimal floorplan with the minimum cost of peak temperature, wirelength, and area at 6% TTSV area overhead. The peak temperature is reduced from 116 °C to 100 °C with only a 3.5% increase in wirelength. Our floorplan optimization method can provide effective thermal management solutions to 3-D ICs. [ABSTRACT FROM AUTHOR]

Multiple memory stacks can be integrated with a processor chip in the silicon interposer technology ("2.5D" stacking). In 2.5D architecture, there are two different network layers for both coherence and memory traffic. The CPU layer is used for coherence Core-to-Core traffic, while the interposer layer is associated with Core-to-Memory blocks traffic regularly. A load balancing strategy balances the traffics on the two network layers and optimizes the resources utilization. In the aforementioned strategy, after detecting congestion in the CPU layer, packets can be moved to the interposer one. It can be concluded that this transferring encounters the bottleneck of the edge portion that is connected to memory blocks. In this paper, we propose a Controlled Load Balancing Mechanism (CLBM) which efficiently controls bottleneck in load balancing methods. As a result, the CLBM selects an appropriate network based on the destination address without comparing latencies of two networks. Moreover, a multicast fault-tolerant ring is introduced to propagate network congestion information. The experimental results showed that, as compared with the absence of load balancing method and traditional load balancing strategy, our CLBM strategy achieves 37.82% and 17.22% average latency improvements and 22.19% and 8.55% average total power with minor overhead. [ABSTRACT FROM AUTHOR]

Selection strategy is an essential part of an adaptive routing algorithm that influences the performance of the networks‐on‐chip (NoC). A selection strategy is used for selecting the best output channel from the available channels according to the network status. This study presents a new output selection strategy called destination intensity and congestion aware (DICA) that uses both local and regional congestion information from adjacent and two hops away neighbours on the path to destination based on the channel and switch information. Also, the proposed output selection strategy uses a new global congestion‐aware scheme based on destination node called destination congestion awareness method to distribute traffic more equally over the network. The simulation results show that DICA strategy consistently improves the performance in both throughput and average latency with minimal overhead in terms of area consumption for various synthetic and real application traffic patterns. In addition, the microarchitecture of NoC routers is also presented in this study and it shows that the proposed output selection strategy can be combined with any adaptive routing algorithms. The experimental results show the average delay improvements of DICA to the Bufferlevel, neighbours‐on‐path, and regional congestion awareness are 87, 57, and 24%, respectively. [ABSTRACT FROM AUTHOR]

Highlights • BC-NoC is an efficient method to reduce network packet latency. • Proposed RIP BC-NoC partitioning method enhances workload consolidation density. • Task communication minimally uses other application resources. • Application tasks can be mapped close to each other in a straight path. • Increased consolidation density & reduced latency improve performance parameters. Abstract The network on a chip (NoC) is considered as the main shared communication resource to avoid compromise the system performance. A strict isolation strategy is employed in the NoC to avoid performance degradation; however, this strategy is accompanied by a low consolidation density or a complex routing mechanism, which leads to considerable latency and high hardware costs. We propose the row irregular partitioning (RIP) method, which results in a high consolidation density compared to regularity-oriented topology. We additionally propose a congestion awareness (CA) mapping scheme in which mapping is performed based on congestion control on a route in a bypass-channel-based NoC (BC-NoC). Furthermore, mapping methods, such as straight path (SP) and straight path and congestion awareness (SP&CA), are recommended to exploit the communication platform properties of BC-NoC. The experimental results show that the average delay in the SP mapping method is improved compared with SP&CA and CA. [ABSTRACT FROM AUTHOR]

Three dimensional Networks-on-Chip (3D NoCs) have evolved as an ideal solution to the communication demands and complexity of future high density many core architectures. However, the design practicality of 3D NoCs faces several challenges such as thermal issues, high power consumption and area overhead of 3D routers as well as high complexity and cost of vertical link implementation. To mitigate the performance and manufacturing cost of 3D NoCs, inhomogeneous architectures have emerged to combine 2D and 3D routers in 3D NoCs producing lower area and energy consumption while maintaining the performance of homogeneous 3D NoCs. Due to the limited number of vertical links, application mapping on inhomogeneous 3D NoCs can be complex. However, application mapping has a great impact on the performance and energy consumption of NoCs. This paper presents an energy and performance aware application mapping algorithm for inhomogeneous 3D NoCs. The algorithm has been evaluated with various realistic traffic patterns and compared with existing mapping algorithms. Experimental results show NoCs mapped with the proposed algorithm have lower energy consumption and significant reduction in packet delays compared to the existing algorithms and comparable average packet latency with Branch-and-Bound. [ABSTRACT FROM AUTHOR]

In this paper, we propose an energy-efficient reconfigurable platform for in-memory processing based on novel four-terminal spin Hall effect-driven domain wall motion devices that could be employed as both nonvolatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to system level simulation results show that, with 28% area increase in memory structure, the proposed in-memory processing platform achieves a write energy ~15.6 fJ/bit with 79% reduction compared to that of SOT-MRAM counterpart while keeping the identical 1 ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3%, as compared with the recent nonvolatile in-memory logic designs. An extensive reliability analysis is also performed over the proposed circuits. We employ advanced encryption standard (AES) algorithm as a case study to elucidate the efficiency of the proposed platform at application level. Simulation results exhibit that the proposed platform can show up to 75.7% and 30.4% lower energy consumption compared to CMOS-ASIC and recent pipelined domain wall (DW) AES implementations, respectively. In addition, the AES energy-delay product can show 15.1% and 6.1% improvements compared to the DW-AES and CMOS-ASIC implementations, respectively. [ABSTRACT FROM AUTHOR]

The movement toward 3D fabrication coupled with Network-on-Chip (NoC) aims to improve area, performance, power, and scalability of many-core systems. However, reliability issue as a perpetual challenge in advanced silicon technology imperils it. Aging is an emerging reliability concern, which degrades the system's performance and causes timing failure eventually. Bias-Temperature-Instability (BTI) and Hot-Carrier-Injection (HCI) are the dominant aging mechanisms, which escalate in high temperature and stress (i.e., usage). In addition to the intra-layer temperature variations, 3D NoCs experience inter-layer temperature variations, which demand necessary investigations for aging as compared to 2D NoC. In this paper, we propose AROMa, an aging-aware deadlock-free adaptive routing algorithm integrated with a novel online aging monitoring system for 3D NoCs. The monitoring system in AROMa exploits Distributed-Centralized-Aging-Table (D-CAT) to obtain routers’ aging rates for each layer of 3D NoCs periodically. Consequently, AROMa swaps between different k-best source-destination shortest paths periodically to avoid highly aged routers, force them in recovery phase of BTI, and accordingly balance aging in the network. We prove that AROMa is deadlock free. Our extensive experimental analysis using gem5 full system mode for PARSEC and SPLASH-2 benchmark suites concludes that AROMa outperforms state-of-the-art works while improving age imbalance by 70 percent and maximum age by 35 percent in 3D NoC with negligible overheads. [ABSTRACT FROM AUTHOR]

In the movement from a multi‐core to a many‐core era, cores count on the chip increases quickly thus interconnect plays a large role in achieving the desired performance. Network‐on‐chip (NoC) is the most widely used interconnect as a scalable alternative for traditional shared bus in many‐core chips. As the dimensions of mesh‐based NoC increase, routers and links serve as a major part to achieve the desired performance and low‐latency communication between cores. In this study, the authors propose an arbitration mechanism for NoC that leads to a reduction in congestion delay in routers as well as the network latency. The proposed mechanism is compatible with the bypass and baseline pipeline in routers. System simulations with Noxim demonstrate reduction in latencies and power consumption using different routing algorithms for 4×4,8×8 and 16×16 mesh topologies, as compared with a baseline router. [ABSTRACT FROM AUTHOR]

Recently, Through-Silicon-Via (TSV) has been more popular to provide faster inter-layer communication in three-dimensional Networks-on-Chip (3D NoCs). However, the area overhead of TSVs reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs such as homogeneous 3D NoCs topologies. Also, 3D routers require more memory and thus they are more power hungry than conventional 2D routers. Alternatively, hybrid 3D NoCs combine both the area and performance benefits of 2D and 3D router architectures by using a limited number of TSVs. Existing hybrid architectures suffer from higher packet delays as they do not consider the dynamic communication patterns of different application and their NoC resource usage. We propose a novel algorithm to systematically generate hybrid 3D NoC topologies for a given application such that the vertical connections are minimized while the NoC performance is not sacrificed. The proposed algorithm analyses the target application and generates hybrid architectures by efficiently redistributing the vertical links and buffer spaces based on their utilizations. Furthermore, the algorithm has been evaluated with synthetic and various real-world traffic patterns. Experimental results show that the proposed algorithm generates optimized architectures with lower energy consumption and a significant reduction in packet delay compared to the existing solutions. [ABSTRACT FROM PUBLISHER]

Reliability is one of the most challenging problems in the context of three-dimensional network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the manufacturing process in order to prevent costly redesigns of a target system. This article classifies the potential physical faults of a baseline TSV-based 3D NoC architecture by targeting two-dimensional (2D) NoC components and their inter-die connections. In this paper, through-silicon via (TSV) issues, thermal concerns, and single event effect (SEE) are investigated and categorized, in order to propose evaluation metrics for inspecting the resiliency of 3D NoC designs. A reliability analysis for major source of faults is reported in this article separately based on their mean time to failure (MTTF). TSV failure probability induced by inductive and capacitive coupling is also discussed. Finally, the paper provides a formal reliability analysis on the aggregated faults that affect TSV. This formal analysis is critical for estimating the resiliency of different components in order to mitigate the redundancy cost of fault-tolerant design or to examine the efficiency of any proposed fault-tolerant methods for 3D NoC architectures. [ABSTRACT FROM PUBLISHER]

Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long-distance communication among processing elements. To solve these limitations, we employed on-chip wireless communication as express links for transferring data so that transfer latency can be reduced. A hybrid NoC architecture utilizing both wired and wireless communication approaches is proposed in this paper. We also devised a deadlock-free routing algorithm that is able to make efficient use of the incorporated wireless links. Moreover, simulated annealing optimization techniques were applied to find optimal locations for wireless routers. Cycle-accurate simulation results showed a significant improvement in transfer latency. Area and power consumption analysis demonstrates the feasibility of our proposed NoC architecture. [ABSTRACT FROM AUTHOR]

Efficient on-chip communication is necessary for exploiting enormous computing power available on a many-core chip. Routing algorithms play a major role for the communication quality and performance of the on-chip interconnection networks. This paper proposes TagNoC, as an on-chip network router architecture with novel hybrid routing approach which reduces latency and power consumption at a fixed cost based on information redundancy. TagNoC is a hybrid routing approach which combines the source and distributed routing methods together. While eliminating packet routing in each router, TagNoC determines the forwarding output port in parallel with input buffering. For a marginal cost increase in header size, as compared to distributed routing techniques, routing latency can be hidden while eliminating power consuming portion of the routing, increasing router throughput and decreasing latency. The proposed TagNoC router is compared to baseline router with distributed routing implementation on a 16-node CMP mesh. Physical implementation of all routers is modeled using synthesized RTL, detailed area analysis, and accurate channel models. Performance evaluation is also carried out utilizing RTL simulation and detailed power analysis on both synthetic and application traffic is performed using post-synthesis gate-level simulation. The simulation results illustrate that TagNoC outperforms as compared to baseline distributed architecture and other source routing methods in terms of power, latency, and throughput. [ABSTRACT FROM AUTHOR]

We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between -1 and 1 after each convolutional layer, and this leaves one bit unused in half-precision floating-point representation. By taking advantage of the unused bit, we create a backup for the most significant bit to protect it against the soft errors. Also, considering the fact that in MLC STT-RAMs the cost of memory operations (read and write), and reliability of a cell are content-dependent (some patterns take larger current and longer time, while they are more susceptible to soft error), we rearrange the data block to minimize the number of costly bit patterns. Combining these two techniques provides the same level of accuracy compared to an error-free baseline while improving the read and write energy by 9% and 6%, respectively. [ABSTRACT FROM AUTHOR]

Silent Data Corruptions (SDCs), those errors that escape detection methods, are critical for system designers because they may result in systems failures. In order to catch SDCs, mechanisms should focus on the behavioural aspects of errors in addition to their physical location or error patterns. Therefore, protection codes like parity, hamming, and the Reed-Solomon code, which heavily depend on the physical location of data bits, are not enough in processors for detection of computing errors. Using characterizing data behaviour during program executions, we have observed value locality in results of destination register for each instruction binary code (instruction opcode and operand codes). This locality exists not only in the results of each instruction, but also in the results of instructions at different memory locations having the same binary code. As a result, an architecture called Instruction Result History Table (IRHT) is presented, which is indexed by the instruction binary code. In the IRHT, a history of values produced by the same instruction binary codes are stored in and utilized during each instruction execution cycle. Any mismatch between the stored values in the IRHT and those generated by current execution, indicates an SDC syndrome. To confirm having SDCs with a high level of confidence, a second execution of the current instruction is issued. A duplication of the execution confirms whether SDC occurred. In the case of SDCs, a third instruction execution with the help of a majority voting frees the system of SDC. Several extensive simulations showed that, up to 83.54% of SDCs are detectable with the help of this locality. Moreover, with the small hardware, IRHT, i.e., 16 kB size, 80.66% of SDCs can be detected on average. Note that the presented method can detect those errors that escape conventional detection mechanisms. So, it can be utilized in conjunction with other conventional methods. [ABSTRACT FROM AUTHOR]

Deep neural networks are widely used in many artificial intelligence applications. They have demonstrated state-of-the-art accuracy on many artificial intelligence tasks. For this high accuracy to occur, deep neural networks require the right parameter values. This is achieved by a process known as training. The training of large amounts of data via many iterations comes at a high cost in regard to computation time and energy. Optimal resource allocation would therefore reduce the training time. TensorFlow, a computational graph library developed by Google, alleviates the development of neural network models and provides the means to train these networks. In this article, we propose Adaptive HTF-MPR to carry out the resource allocation, or mapping, on TensorFlow. Adaptive HTF-MPR searches for the best mapping in a hybrid approach. We applied the proposed methodology on two well-known image classifiers: VGG-16 and AlexNet. We also performed a full analysis of the solution space of MNIST Softmax. Our results demonstrate that Adaptive HTF-MPR outperforms the default homogeneous TensorFlow mapping. In addition to the speed up, Adaptive HTF-MPR can react to changes in the state of the system and adjust to an improved mapping. [ABSTRACT FROM AUTHOR]

Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate for next generation memory as it is non-volatile, fast, and has unlimited endurance. Another important aspect of STT-MRAM is that its core component, the nanoscale magnetic tunneling junction (MTJ), is thought to be radiation hard, making it attractive for space and nuclear technology applications. However, studies on the effects of ionizing radiation on the STT-MRAM writing process are lacking for MTJs with perpendicular magnetic anisotropy (pMTJs) required for scalable applications. Particularly, the question of the impact of extreme total ionizing dose on perpendicular magnetic anisotropy, which plays a crucial role on thermal stability and critical writing current, remains open. Here we report measurements of the impact of high doses of gamma and neutron radiation on nanoscale pMTJs used in STT-MRAM. We characterize the tunneling magnetoresistance, the magnetic field switching, and the current-induced switching before and after irradiation. Our results demonstrate that all these key properties of nanoscale MTJs relevant to STT-MRAM applications are robust against ionizing radiation. Additionally, we perform experiments on thermally driven stochastic switching in the gamma ray environment. These results indicate that nanoscale MTJs are promising building blocks for radiation-hard non-von Neumann computing. [ABSTRACT FROM AUTHOR]

The magnesium oxide (MgO) adhesion layer is proposed to avoid adverse effects of lossy metallic adhesion layers in thin film plasmonic nanostructures. Such adverse effects can be in the form of resonance broadening and a decrease in the resonance magnitude. We fabricate and test the quality of MgO adhesion layers and determine its optical properties through ellipsometry measurements. We also provide the plasmonic response of various plasmonic nanostructures (nanohole array, nanodisk array, dimer nanohole array, and bowtie slot antenna array) with a MgO adhesion layer and conventional adhesion layers including titanium (Ti), chromium (Cr), tantalum (Ta), and indium tin oxide (ITO). Our results show that unlike conventional adhesives, MgO has almost no adverse effect on the plasmonic resonance of the designed nanostructures. [ABSTRACT FROM AUTHOR]

The balanced ternary representation allows for significant performance improvement for ternary systems. Immaturity of the semiconductor industry in providing an applicable device for ternary infrastructures during the past decades is an enormous obstacle to actualize the ternary circuit realization. Among the promising devices for this purpose, carbon nanotube field effect transistor (CNFET) is qualified with outstanding characteristics which make it suitable for implementing the ternary logic functions. In this paper, for the first time, we present and evaluate the basic ternary arithmetic circuits in balanced representation based on the CNFET technology. Experimental evaluation of reviewed designs in both balanced and unbalanced representation indicates the superiority of the balanced representation in the design of ternary arithmetic blocks. [ABSTRACT FROM AUTHOR]

This paper proposes energy-efficient approximate multipliers based on the Mitchell's log multiplication, optimized for performing inferences on convolutional neural networks (CNN). Various design techniques are applied to the log multiplier, including a fully-parallel LOD, efficient shift amount calculation, and exact zero computation. Additionally, the truncation of the operands is studied to create the customizable log multiplier that further reduces energy consumption. The paper also proposes using the one's complements to handle negative numbers, as an approximation of the two's complements that had been used in the prior works. The viability of the proposed designs is supported by the detailed formal analysis as well as the experimental results on CNNs. The experiments also provide insights into the effect of approximate multiplication in CNNs, identifying the importance of minimizing the range of error.The proposed customizable design at $w$w = 8 saves up to 88 percent energy compared to the exact fixed-point multiplier at 32 bits with just a performance degradation of 0.2 percent for the ImageNet ILSVRC2012 dataset. [ABSTRACT FROM AUTHOR]

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency. [ABSTRACT FROM AUTHOR]

3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. To reliably route packets under such conditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected 3D-NoCs named First-Last. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the East and North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layers is available anywhere in the network. An improved version of our algorithm, named Enhanced-First-Last is also introduced and shown to dramatically improve performance under low TSV availability while still using less virtual channels than state-of-the-art algorithms. A comprehensive evaluation of the cost and performance of our algorithms is performed to demonstrate their merits with respects to existing solutions. [ABSTRACT FROM AUTHOR]

2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin. [ABSTRACT FROM AUTHOR]

In modern many-core architectures, advanced on-chip networks provide the means of communication for the cores. This greatly complicates the design and verification of the cache coherence protocols deployed by those cores. A common approach to deal with this complexity is to decompose the whole system into the protocol and the network. This decomposition is, however, not always possible. For example, unexpected deadlocks can emerge when a deadlock-free protocol and a deadlock-free network are combined. This paper proposes a compositional methodology: prove properties over a network, prove properties over a protocol, and infer properties over the system as a whole. Our methodology is based on theorems that show that such decomposition is possible by having sufficiently large local buffers at the cores. We apply this methodology to verify several protocols such as MI, MSI, MESI and MEUSI running on top of advanced interconnects with adaptive routing. [ABSTRACT FROM AUTHOR]

Backgrounds: Nowadays developing smart and fast services for patients and transforming hospitals to modern hospitals is considered a necessity. Living in the world inundated with information systems, designing services based on information technology entails a suitable architecture framework.Objectives: This paper aims to present a localized enterprise architecture framework for the Iranian university hospital.Methods and Results: Using two dimensions of implementation and having appropriate characteristics, the best 17 enterprises frameworks were chosen. As part of this effort, five criteria were selected according to experts' inputs. According to these criteria, five frameworks which had the highest rank were chosen. Then 44 general characteristics were extracted from the existing 17 frameworks after careful studying. Then a questionnaire was written accordingly to distinguish the necessity of those characteristics using expert's opinions and Delphi method. The result showed eight important criteria. In the next step, using AHP method, TOGAF was chosen regarding having appropriate characteristics and the ability to be implemented among reference formats. In the next step, enterprise architecture framework was designed by TOGAF in a conceptual model and its layers. For determining architecture framework parts, a questionnaire with 145 questions was written based on literature review and expert's opinions. The results showed during localization of TOGAF for Iran, 111 of 145 parts were chosen and certified to be used in the hospital.Conclusion: The results showed that TOGAF could be suitable for use in the hospital. So, a localized Hospital Enterprise Architecture Modelling is developed by customizing TOGAF for an Iranian hospital at eight levels and 11 parts. This new model could be used to be performed in other Iranian hospitals. [ABSTRACT FROM AUTHOR]

This paper presents two new ternary operators which can be used in different scrambling crypto algorithms. The employment of the proposed operators ( ScramOp1 and ScramOp2 ) leads to reduction in the number of decoding steps, equivalent to only one operation per digit for the receiver side. These operators are presented for the first time in ternary logic. There are some other ternary operators such as SUM , which are specifically suitable for computer arithmetic but they lack desirable efficiency for cryptographic applications. The transistor-level designs of the operators are simulated by using Synopsys HSPICE with 32 nm bulk-CMOS technology. Simulation results demonstrate that ScramOp1 and ScramOp2 achieve significant saving in energy consumption (2.11% and 12.14%) in comparison with SUM . Additionally, ScramOp2 requires only 52 transistors while 58 and 60 transistors are needed to implement ScramOp1 and SUM , respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a highly scalable sensor design for late transition detection in FPGA based platforms. Transition delays occur because of aging mechanisms such as Biased Temperature Instability (BTI) and Hot Carrier Injection (HCI). We propose a sensor clock (SCLK) that is a function of minimum slack time of a set of paths selected for age monitoring. There will be one such clock for many sensors as are needed in an entire FPGA. Our proposed sensor architecture makes it possible for a single SCLK to be shared by all sensors. Additionally, the proposed sensor occupies one slice (basic FPGA logic block), which leads to low area, power, and performance overhead. Using Artix-7-based board, experimental results demonstrate that the proposed aging sensor detects aging earlier than existing sensors and provides less power and performance overheads. [ABSTRACT FROM AUTHOR]

Nanotechnologies, notably quantum-dot cellular automata, have achieved world-wide attentions for their prominent features as compared to the conventional CMOS circuitry. Quantum-dot cellular automata, particularly owning to its considerable reduction in size, energy consumption and latency of circuits, is considered as a potential alternative for the CMOS technology. Considering the manufacturing aspects, in this paper, a method is proposed for designing efficient quantum-dot cellular automata circuits. We inspect an alternative approach for streamlined design of quantum-dot cellular automata circuits such that the required external fixed inputs are substantially reduced. In order to demonstrate the efficiency of the proposed method, the widely used multiplexer, XOR and party generator circuits are considered as case studies. All of the proposed circuits are simulated and verified using QCADesigner which is a valid and popular simulation tool. Comparisons indicate that the proposed method considerably reduces the number of external fixed inputs which simplifies the overall circuit implementation and fabrication. [ABSTRACT FROM AUTHOR]

Cache coherence plays a major role in manycore systems. The verification of deadlocks is a challenge in particular, because deadlock freedom is an emerging property. Formal methods often decouple verification of the protocol from verification of the communication interconnect. Modern communication fabrics, however, become more advanced and include a network topology, routing, arbitration, synchronization, and more. In this paper, an integrated approach is proposed that allows cross-layer verification of both the cache coherence protocol and the communication fabric all at once. An automated methodology for deriving cross-layer invariants is proposed. These invariants relate the state of the application-layer protocols to en route packets in the communication fabric. Using the invariants, we derive formal proofs of deadlock-freedom for two case studies: a directory-based MI protocol in a 2D mesh, and a ring-based snoopy protocol in a 2D torus. Additionally, we show that our methodology can be used to derive the smallest possible queue sizes that ensure absence of deadlocks. Our methodology is generally applicable and shows promising scalability. [ABSTRACT FROM PUBLISHER]

Recently, Multiple Valued Logic (MVL) has attracted attention, because it reduces the area and complexity of circuits when compared to binary logic. Carbon nanotube field effect transistors (CNFET) are a good candidate for implementing MVL logic circuits, since determining the threshold voltage value of CNFET is easily achievable by changing the diameter of the nanotubes which are placed under the transistor gate. In this paper, quaternary CNFET based 4–2 and 5–2 compressor cells have been proposed. The proposed cell designs were investigated using HSPICE simulator with the standard 32 nm CNFET technology under different operational conditions such as different temperatures, different load capacitances, and different supply voltages. Also the sensitivity to process variations and noise immunity of the proposed designs have been investigated. The proposed quaternary logic designs reduce the delay of the multi operand addition of arithmetic circuits by eliminating the carry propagation overhead. [ABSTRACT FROM AUTHOR]

3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive routing strategy with respect to the communication flow among the cores is crucial while freedom from livelock and deadlock has to be guaranteed. In this paper we introduce a new routing algorithm for partially connected 3D-NoCs. The routing algorithm is adaptive and tolerates the faults on vertical links as compared to the predesigned routing algorithms. Our results show a $40-50\%$ improvement in the fraction of intact inter-level communications when the fault tolerant algorithm is used. This routing algorithm is light-weight and has only one virtual channel along the $Y$ dimension. [ABSTRACT FROM AUTHOR]

This paper presents a novel method for design and implementation of three dimensional (3D) two-layer devices with 1/0 logic values. This method uses carbon nanotube (CNT) technology as well as the molecular quantum cellular automata (MQCA) technology on a graphene substrate. The most significant characteristic of the proposed design, which makes the design unique, is the capability of generating functions in 3D; the proposed method would allow implementation of the designs in a single layer which significantly impacts on reducing the chip area and also greatly facilitates the overall synthesis of the design including placement, routing and reducing the critical path length. [ABSTRACT FROM AUTHOR]

This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based quaternary logic circuits. The proposed quaternary circuits are designed based on the CNTFET unique properties, such as the same carrier mobility for N- and P-type devices and also providing desirable threshold voltages by adopting proper diameters for the nanotubes. In addition, no paths exist between supply and ground rails in the steady states of the proposed designs, which eliminates the ON state static current and also the stacking technique is utilised in order to significantly reduce the leakage currents. The results of the simulations, conducted using Synopsys HSPICE with the standard 32 nm CNTFET technology, confirm the significantly lower power consumption, higher energy efficiency and lower sensitivity to process variation of the proposed designs compared to the state-of-the-art quaternary logic circuits. The proposed quaternary logic circuits have on average 92, 99 and 91% less total power, static power and PDP, respectively, compared with the most low-power and energy-efficient CNTFET-based quaternary logic circuits, recently presented in the literature. [ABSTRACT FROM AUTHOR]

At our institution, percent tumor burden in prostate core biopsies is quantified using variations of one of two methods. Measurement by the Aggregate method reports only adenocarcinoma and omits intervening stroma and benign prostatic glands while the Discontinuous method includes the intervening stroma and benign glands between distinct foci of adenocarcinoma. In this study, we selected cases with 12-part core biopsies that were followed by a radical prostatectomy within two years. Interestingly, we found that when adenocarcinoma involved prostate 12-part core biopsies and subsequent resection unilaterally, there is no significant difference in absolute percentage of tumor using either measuring method ( P = 0.4). In contrast, when adenocarcinoma involved the biopsies unilaterally and subsequent prostatectomy bilaterally, the two measurement methods had a statistically significant difference in percentage scores ( P = 0.002). In the study cohort, other factors including Gleason score ( P = 0.88) and total number of adenocarcinoma-involved cores ( P = 0.27) did not introduce any significant correlation with bilateral involvement. In this study, we found that biopsies that discontinuously and unilaterally involve half of a prostate are much more likely to involve both lobes than those that are unilateral and present in nodular aggregates. [ABSTRACT FROM AUTHOR]

This paper presents a new ternary operator for cyclic redundancy check in ternary logic with high hardware efficiency. It shows the essential properties of a ternary operator for calculating CRC. Gate-level implementation of CRC-16 is exemplified and comprehensively explained in this paper. Transistor-level realizations of the new and the previous operators are also given in full detail. This paper demonstrates that the employment of the proposed operator reduces hardware components such as the elimination of one entire operator in both transmitter and receiver sides in comparison with ternary SUM . In addition, simulation results by HSPICE and 32 nm CNTFET technology shows about 20.6% energy reduction for one of the implementation methods of the proposed operator with respect to the previously presented one ( CCW CYCLE ). Furthermore, five fewer transistors are needed to design the proposed operator in contrast with both operators SUM and CCW . [ABSTRACT FROM AUTHOR]

This paper deals with the bridge-style circuits. They are highly efficient in terms of transistor density per unit of area. They comply with the conventional CMOS style and form a full-swing and robust structure. First, we clarify the necessary conditions under which a Boolean function can be implemented fully symmetrical. Then, it is demonstrated that it is possible to design out of functions fully symmetrical. Eventually, we show how the pull-up and pull-down networks are constructed in a bridge circuit for any three-input function which fulfils the conditions of being implemented fully symmetrical. [ABSTRACT FROM AUTHOR]

As the number of on-chip processor cores increases, power-efficient solutions are sought for data communication between cores. The Helix-h non-blocking photonic switch is developed to improve physical-layer and network performance parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Traffic benchmarks and practical case studies using a cycle-accurate simulation environment indicate significantly reduced insertion loss providing improved bandwidth density and scalability to manycore plurality. Improvements in system performance parameters are quantified for network bandwidth, transmission efficiency, and latency in popular photonic internconnection topologies, in comparison to previous switch designs. For instance, utilizing the Helix-h switch in a mesh topology, the bandwidth is increased by 112 percent compared to the previously highest performing switch design. Execution time and energy efficiency are improved by up to 92 and 99 percent, respectively, for representative multicore applications. Finally, the technique is generalized to a novel graph-theoretic method for articulating blocking conditions in photonic switches. [ABSTRACT FROM AUTHOR]

TSV-to-TSV coupling is known to be a significant detriment to signal integrity in three-dimensional (3D) IC architectures. Designing a reliable Through-Silicon Via is critical in order to support better performance. This paper explores the challenges brought on by capacitive and inductive TSV-to-TSV coupling in TSV-based 3D ICs. Based on our analyses, we propose two approaches to mitigate these effects. In one approach, a novel coding technique that adjusts the current flow pattern is proposed to mitigate the inductive coupling effects. In another approach an alternative architecture, wrapping around the TSVs, is proposed to greatly reduce the capacitive coupling effect. The efficiency of the proposed coding methods and supporting architectures is demonstrated by comprehensive simulations at both the hardware and system levels. [ABSTRACT FROM AUTHOR]

In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs, such as having same mobility for electrons and holes and also capability of adopting desirable threshold voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise margins and higher robustness as compared to the previous CNTFET-based designs. The proposed quaternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42% and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs. [ABSTRACT FROM AUTHOR]

Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very interesting field of research in QCA domain. In this paper, we are going to propose novel nanotechnology-compatible designs based on the majority gate structures. In the first step, this objective is accomplished by QCA implementation of two well-organized JK flip-flop designs and in the second step; synchronous counters with different sizes are presented as an application. To evaluate functional correctness of the proposed designs and compare with state-of-the-art, QCADesigner tool is employed. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) exhibits a new paradigm at nanoscale for possible substitution of conventional CMOS technology. Most of the research works in QCA domain have completely ignored the significance of energy consumption constraint in designing circuits. In this study a low complexity and energy-efficient QCA T flip–flip as well as high-performance single-layer synchronous counters are proposed. By cascading the proposed T flip-flop and a suitable level converter, a QCA-compatible structure for falling edge triggered T flip-flop is achieved. This circuit functions as the chief element for constructing synchronous counters. QCADesigner and QCAPro tools are used for evaluating the functionality and calculating dissipated energy of the circuits, respectively. Results indicate the superiority of the proposed circuits in terms of complexity, latency and energy consumption as compared to their state-of-the-art counterparts. The proposed T flip-flop demonstrates 18% leakage energy improvement besides the considerable value of 56% switching energy improvement in 0.5Ek tunneling energy level as compared to the best ones. It is worth mentioning that 41%, 44% and 45% optimizations in the number of cells in addition to 15%, 25% and 33% optimizations in the area are achieved for the proposed mod 4, mod 8 and mod 16 counters, respectively, in comparison with the best previous results. [ABSTRACT FROM AUTHOR]

This paper investigates the transmission of an injection-locked optical orthogonal frequency-division multiplexing (ILO-OFDM) scheme over an optical fiber. In the ILO-OFDM system, an optically injection-locked semiconductor laser is utilized to directly modulate the OFDM signal on the optical carrier. With a sufficiently large injection strength and a negative shift of the detuning frequency, the modulation sidebands become asymmetric similar to a single sideband modulation (SSB). The SSB spectrum is advantageous for minimizing the chromatic dispersion-induced power variation. Using simulation we show that ILO-OFDM system can be used to compensate for chromatic dispersion in long-haul applications. [ABSTRACT FROM AUTHOR]