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This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential for advanced circuit designs. The results show that VeSFET can provide high I {\mathrm {eff}} to I {\mathrm {off}} ratio, low gate capacitance, high \Delta V {t}/ V { {\textit{g2s}}} , and competitive drive capability with respect to a reference FinFET of comparable dimensions. [ABSTRACT FROM PUBLISHER]

The introduction of FinFET architecture was expected to alleviate the issue of mismatch compared with planar technology, given the lower doping levels required. However, several authors have reported better mismatch results for planar technology suggesting additional challenges for FinFET architecture. An additional mechanism previously not considered arising from charge present at points of disturbance in the silicon lattice in tapering and wavering fins is shown to contribute to transistor mismatch. We show that including this mechanism improves the quantitative understanding of mismatch in FinFETs. [ABSTRACT FROM AUTHOR]

In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts. [ABSTRACT FROM AUTHOR]

Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon–germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage ($\text{V}_{T}$) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage (${I}_{ \mathrm{\scriptscriptstyle OFF}} $) variability and in the halo region at the drain sidewall for $\text{V}_{T}$ variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ random variability for scaled voltages. [ABSTRACT FROM AUTHOR]

Application of high-frequency ac stress in the place of conventional dc stress is known to decrease the damage caused by self-heating (SH)-induced hot-carrier injection (HCI) in highly scaled MOSFET devices. However, the effect of hot-carrier degradation on short-channel performance is less explored. In this article, a detailed examination of the drain-induced barrier lowering (DIBL) under hot-carrier stress is presented for 14-nm silicon-on-insulator (SOI) n-channel FinFETs. In particular, the influence of SH-enhanced HCI on DIBL is thoroughly investigated for devices with different geometrical parameters including a number of fins, gate length, and so on at different ac stress frequencies. The change in dominant degrading mechanism from bulk oxide trapping to interface state generation under dc and ac stress is shown to affect DIBL severely. Interestingly, the effect of SH on DIBL is in contrast to that in ON-current degradation. Furthermore, time evolution of DIBL degradation for asynchronous stress waveforms is studied for accurate reliability analysis for short-channel devices. [ABSTRACT FROM AUTHOR]

Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

Vertically stacked junctionless accumulation mode (JLAM) nanowire field effect transistors (NWFETs) outperform inversion-mode (IM) NWFETs below 10-nm technology nodes, but the vertical stacking of nanowires (NWs) has a constraint of position dependent drain current. This paper encompasses: 1) extensive investigation of the impact of series resistance on IM, JL mode, and JLAM NWFET architectures; 2) a proposed approach to mitigate the series resistance; and 3) linearity assessment of stacked JLAM-NWFET for radio frequency (RF) applications. We have suggested that by decreasing the channel doping in the bottom NW with respect to the top NW in a stack, the current can be significantly improved along with the reduction in series resistance. This improves the overall uniformity of drain current in each NW for stacked JLAM-NWFET. The linearity performance of the device is assessed in terms of following figure of merits (FOMs): IIP3, 1-dB compression point, and higher order derivative of transconductance ${g}_{m\textsf {2}}$ and ${g}_{m\textsf {3}}$. These FOMs are evaluated through numerical simulations using Sentaurus Technology Computer-Aided Design to confirm the robustness of the device against intermodulation distortion making it suitable for low power radio frequency integrated circuit design applications. The proposed solution allows higher drive current, improved linearity, and thus lower distortion in stacked JLAM-NWFET. [ABSTRACT FROM AUTHOR]

Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for realization of advanced CMOS technology nodes. Due to small nanowire dimensions, NWFETs are vulnerable to the impact of process-induced random local variations, such as the line edge roughness (LER) and random dopant fluctuation (RDF). NWFETs have three different device modes, namely, the inversion mode (IM), the accumulation mode (AM), and the junctionless (JL) mode. In this paper, a 3-D quasiatomistic LER model is used for the analysis of LER-induced mismatch in JL, IM, and AM NWFETs. We have also compared the impact of 3-D LER with that of 2-D LER. In addition, another emerging simulation methodology known as statistical impedance field method is utilized to analyze the impact of RDF on the three flavors of NWFETs. We show that JL NWFETs have much higher mismatch due to both LER and RDF than their IM and AM NWFET counterparts with otherwise identical device structure. [ABSTRACT FROM AUTHOR]

We investigate the channel material dependence of wave function deformation scattering (WDS), a phenomenon that occurs when the shape of the carrier wave function is forced to change as the channel is traversed. Line-edge roughness (LER) is one nonideality that can induce WDS in confined device geometries. We perform nonequilibrium Green's function simulations of ensembles of ultrascaled Fin Field Effect Transistors that exhibit correlated LER to determine the resulting on-current distributions. By considering various channel materials, we demonstrate two trends. First, WDS has a greater impact when the transport effective mass of the channel material is low, due to stronger coupling between conducting subbands. Second, WDS has a greater impact when the confinement effective mass of the channel material is high, due to the presence of more conducting subbands, which further enhances coupling. [ABSTRACT FROM AUTHOR]

An analytical model of parasitic capacitancein inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness (Tiox) and inserted-oxide recess (Trec), is shown using the proposed model and TCAD simulations. [ABSTRACT FROM AUTHOR]

We examine the impact of line-edge roughness (LER) on the variability in the on-current and saturation threshold voltage of ultrascaled FinFET devices via quantum-mechanical transport simulation. We obtain a realistic model of LER by decomposing the LER into short- $\lambda $ and long- $\lambda $ fluctuations, and we consider their separate influences on device performance. We show that the long- $\lambda $ fluctuations lead to greater device variability than the short- $\lambda $ fluctuations, and we explain the difference between the two cases via the influence of fluctuating quantum confinement arising from the LER. Finally, we consider devices in which the long- $\lambda $ fluctuations of the two fin edges are correlated and demonstrate that this correlation significantly improves the variability. Thus, we show the continued need for fabrication technology either to reduce the amplitude of the long- $\lambda $ fluctuations or to ensure the long- $\lambda $ fluctuations between the sidewalls of ultrascaled FinFET devices are correlated. [ABSTRACT FROM AUTHOR]

Recently, negative-capacitance FETs (NCFETs) have been proposed to reduce subthreshold slope and help continue supply-voltage scaling alongside channel-length scaling. We investigate the high-frequency switching behavior of NCFETs using the Landau–Khalatnikov equation to model ferroelectric materials. Multidomain interactions in the ferroelectric are considered, resulting in strong agreement with experimental measurements. Operation of NCFETs at gigahertz frequencies is investigated with this experimentally validated multidomain model. We find that the effectiveness of the voltage amplification in NCFETs is strongly dependent on the viscosity coefficient $\rho $ of the ferroelectric, and that a low \rho $ ( <0.1~\Omega \cdot \text {m} ) is required for the operation at the high gigahertz frequencies. [ABSTRACT FROM PUBLISHER]