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After the development of TLC (Triple level cell) NAND, QLC (Quad level cell) technology will be one of the solutions for next generation NAND flash product. QLC (4 bits/cell) NAND's data levels are up to 16 levels which bring the narrower and tighter voltage ranges and worse performance. This paper studies QLC program and read mechanisms, and presents five types of program algorithms for writing data in QLC cells. Correspondingly, the enhanced Gray coding methods for data mapping based on these different program algorithms are researched. They will be beneficial to data reading. After simulating with changing cell voltages to generate the data errors in the QLC model, the paper presents four enhanced Gray codings to match 16 voltage levels for different program algorithms and read operations. This study will improve the efficiency and keep balance in system-level application for the data error correction of QLC 4 pages which are mapped in the same wordline (WL). [ABSTRACT FROM AUTHOR]

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width = 82.9 nm/8.6 nm) have been developed after integrating a 14 Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. The drive current (I ON ), off current (I OFF ), subthreshold swing (SS), drain-induced barrier lowering (DIBL) and transistor gate delay of 30 nm gate length (L g ) of FinFETs illustrate the promising device performance. The TCAD simulations demonstrate that both threshold voltage (V th ) and off current can be adjusted appropriately through the full silicidation (FUSI) of CoSi 2 gate engineering. Moreover, the drive currents of n- and p-channel FinFETs are able to be further enhanced once applying the raised Source/Drain (S/D) approach technology for reducing the S/D resistance drastically. [ABSTRACT FROM AUTHOR]

A wideband low‐phase noise VCO is proposed for multi‐standard wireless communication system. An 8‐shaped high‐Q inductor is employed to enhance the performance of the VCO. The frequency pulling is reduced by using the 8‐shaped coil. Implemented in a 180 nm CMOS process, the VCO can provide a very wide tuning range of 65.4% from 2.49 to 4.91 GHz. A phase noise lower than −121.25 dBc/Hz is obtained at 1 MHz offset over the whole working band while the current consumed varies from 3.5 to 8.7 mA. [ABSTRACT FROM AUTHOR]

Summary: A high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2. [ABSTRACT FROM AUTHOR]

A low-cost regulator insensitive to temperature and supply voltage variations for power management units of Radio Frequency Identification (RFID) tag chips and other batteryless devices is proposed in this paper. The commonly used regulator has poor temperature rejection ratio (TRR) and poor voltage rejection ratio (VRR). By using combination resistors and long channel transistors, the bias and regulator circuits are improved over temperature variations. A power supply rejection (PSR) enhancement branch is also added to suppress the supply noise and stabilize the bias current. The regulator is designed and fabricated in the HJTC 0.25m CMOS technology. Simulation results show that this regulator achieves 0.044mV/C TRR when temperature varies from C to 70C and 1.1mV/V VRR while the supply voltage of the regulator ranges from 4 to 12V. The PSR is nearly 100dB at DC. The area of this regulator is 0.102mm2 including the bias circuit. The measurement results meet simulation results well and this regulator is successfully applied in HF passive tag chips within voltage deviations of of 2.5V. [ABSTRACT FROM AUTHOR]

Elliptic curve cryptography (ECC) has been widely used for the digital signature to ensure the security in communication. It is important for the ECC processor to support a variety of ECC standards to be compatible with different security applications. Thus, a flexible processor which can support different standards and algorithms is desired. In this paper, an efficient and flexible dual-field ECC processor using the hardware–software approach is presented. The proposed processor can support arbitrary elliptic curve. An elaborate modular arithmetic logic unit is designed. It can perform basic modular arithmetic operations and achieve high efficiency. Based on our designed instruction set, the processor can be programmed to perform various point operations based on different algorithms. To demonstrate the flexibility of our processor, a point multiplication algorithm with power analysis resistance is adopted. Our design is implemented in the field-programmable gate array platform and also in the application-specified integrated circuit. After implemented in the 55 nm CMOS process, the processor takes between 0.60 ms (163 bits ECC) and 6.75 ms (571 bits ECC) to finish one-point multiplication. Compared to other related works, the merits of our ECC processor are the high hardware efficiency and flexibility. [ABSTRACT FROM PUBLISHER]

Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((22)2)2), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm2, respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously. [ABSTRACT FROM AUTHOR]

Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track of a mobile robot's location. Correlative Scan Matching (CSM) is a scan matching algorithm for obtaining the posterior distribution probability for the robot's pose in SLAM. This paper combines the non-linear optimization algorithm and CSM algorithm into an NLO-CSM (Non-linear Optimization CSM) algorithm for reducing the computation resources and the amount of computation while ensuring high calculation accuracy, and it presents an efficient hardware accelerator design of the NLO-CSM algorithm for the scan matching in 2D LiDAR SLAM. The proposed NLO-CSM hardware accelerator utilizes pipeline processing and module reusing techniques to achieve low hardware overhead, fast matching, and high energy efficiency. FPGA implementation results show that, at 100 MHz clock, the power consumption of the proposed hardware accelerator is as low as 0.79 W, while it performs a scan match at 8.98 ms and 7.15 mJ per frame. The proposed design outperforms the ARM-A9 dual-core CPU implementation with a 92.74% increase and 90.71% saving in computing speed and energy consumption, respectively. It has also achieved 80.3% LUTs, 84.13% FFs, and 20.83% DSPs saving, as well as an 8.17× increase in frame rate and 96.22% improvement in energy efficiency over a state-of-the-art hardware accelerator design in the literature. ASIC implementation in 65 nm can further reduce the computing time and energy consumption per scan to 5.94 ms and 0.06 mJ, respectively, which shows that the proposed NLO-CSM hardware accelerator design is suitable for resource-limited and energy-constrained mobile and micro robot applications. [ABSTRACT FROM AUTHOR]

For very high frequency (VHF) class Φ2 inverter, conventional design method requires complex tuning for parameters. Without fully quantitative calculations, the tuning highly depends on experience that cannot achieve optimal design. In this article, a target function design strategy is proposed based on quantitative harmonic weighting, which simplifies the design procedures and minimizes the switch voltage stress. First, the target switch voltage with minimized peak value is derived by optimizing the harmonic weighting. With the result, the power switch is modeled as a voltage source to simplify the calculations, where the branch currents are solved to provided fully quantitative analysis. Based on the analysis, optimal features of switching node impedance are derived to achieve the target switch voltage. In addition, basic constrains of the resonant tank are analyzed to reduce circling currents. Combining the optimal features and basic constrains of the resonant tank, the circuit parameters are calculated directly, which minimizes the switch voltage stress and improves power efficiency. Compared with conventional design, a 27.12 MHz prototype demonstrates 10.2% reduction in average switch voltage stress and 7.2% improvement in average efficiency. [ABSTRACT FROM AUTHOR]

Analog arithmetic operations are the most fundamental mathematical operations used in image and signal processing as well as artificial intelligence (AI). In‐memory computing (IMC) offers a high performance and energy‐efficient computing paradigm. To date, in‐memory analog arithmetic operations with emerging nonvolatile devices are usually implemented using discrete components, which limits the scalability and blocks large scale integration. Here, a prototypical implementation of in‐memory analog arithmetic operations (summation, subtraction and multiplication) is experimentally demonstrated, based on in‐memory electrical current sensing units using spin‐orbit torque (SOT) devices. The proposed structures for analog arithmetic operations are smaller than the state‐of‐the‐art complementary metal oxide semiconductor (CMOS) counterparts by several orders of magnitude. Moreover, data to be processed and computing results can be locally stored, or the analog computing can be done in the nonvolatile SOT devices, which are exploited to experimentally implement the image edge detection and signal amplitude modulation with a simple structure. Furthermore, an artificial neural network (ANN) with SOT devices based synapses is constructed to realize pattern recognition with high accuracy of ≈95%. [ABSTRACT FROM AUTHOR]

This paper presents a new method based on a sensor network for designing a lighting control system for an industrial building. An illumination mapping between the work plane and the horizontal plane was derived for sensor placement to generate rules for sensor layout. Online sensor data sampling and a control center database with a real-time update algorithm were applied to lessen the effects of interference and luminous decay. We implemented the method for the lighting system of an industrial building in Xi’an, China. Skylights combined with artificial lighting were designed for daytime lighting. The optimized placement and a scene-control strategy for the artificial lighting system were generated by simulations with DIALux and Autodesk Ecotect Analysis. Daily lighting consumption data for August, 2014, demonstrated that the control system strategy realized lighting energy savings of up to an average of 80% on cloudy days. The design can be used as a reference for new industrial construction or retrofit applications. [ABSTRACT FROM AUTHOR]

—In this paper, a class-F 23 VCO using nonlinear-capacitance transforming technique to simultaneously achieve low phase noise and a wide tuning range is proposed. The phase noise degradation due to the nonlinearity of the switched capacitor in the class-F 23 oscillator is analyzed and quantitatively derived. The phase noise contributed by the nonlinear capacitance can be suppressed by using the proposed nonlinear-capacitance transformation technique. In order to achieve low phase noise over a wide bandwidth, the asymmetric-toggling method is utilized to achieve optimal capacitance ratios across the entire frequency range. Implemented in a 40-nm CMOS process, the proposed oscillator exhibits 41.2 % tuning range from 2.58 GHz to 3.92 GHz while consuming 13.8 mW–14.9 mW power dissipation. The phase noises at 2.58 GHz and 3.92 GHz oscillation frequencies are −136.4 dBc/Hz and −129.6 dBc/Hz at 1-MHz offset. The minimum phase noise is −157.2 dBc/Hz at 10 MHz offset, corresponding to an FoM of 194.1 dBc/Hz and FoM T of 206.4 dBc/Hz. [ABSTRACT FROM AUTHOR]

This paper presents a fractional- N all-digital phase-locked loop (ADPLL). A 4-bit multi-delay line time-to-digital converter (MDL-TDC) using path selection technique is proposed to achieve a 4-ps resolution with 0.24-mW power consumption at 52 MS/s. A TDC offset calibration method is used to eliminate TDC metastability. An isolated constant-slope digital-to-time converter (ICS-DTC) is utilized to cancel the quantization noise (Q-noise) and achieve true-fractional delay. By tuning DTC compensation, spur and Q-noise are suppressed by 14 dB. To speed up the locking process of the ADPLL, a counter-based coarse PLL is integrated to monitor and compensate for large frequency and phase jump while consuming almost zero power. The proposed ADPLL is implemented in a 40-nm standard CMOS process, occupying a silicon area of 0.36 mm2. When TDC offset calibration is turned on, the in-band noise is suppressed by 20 dB. The measured results show 0.78-ps rms jitter and −40-dBc in-band fractional spur are achieved, corresponding to a figure of merit (FOM) of −235 dB. [ABSTRACT FROM AUTHOR]

This article proposes a unified pulsewidth-cycle (UPWC) control strategy to achieve mixed-mode operation and consistent valley switching (VS) for boost power factor correction converter. Compared with conventional single-mode controllers, it has a unified scheme to achieve single discontinuous conduction mode (DCM), single critical conduction mode (CRM), or mixed DCM/CRM operations in each half-line cycle. To regulate the input current as a sinusoid, the UPWC controller adopts a variable pulsewidth and a near-constant switching cycle under DCM, while adopts a constant pulsewidth and a variable switching cycle under CRM. To facilitate analysis, normalized mapping of operation modes is provided, along with the final pulsewidth and switching cycle. Furthermore, to ensure consistent VS, a controlled zero current detection method is proposed to fix the turn-on point of the power switch. No matter in DCM or CRM, consistent VS reduces both the switching loss and current distortion caused by parasitic resonance. To further reduce the current distortion caused by fixing the turn-on point, a compensation gain is provided that reshapes the input current as a sinusoid. Finally, through mixed DCM/CRM operation and consistent VS, the proposed UPWC controller achieves preferable performances in the power range, efficiency, power factor, and current distortion. [ABSTRACT FROM AUTHOR]

Integrators are widely used in industrial controls, signal processing, and computing. However, traditional resistor–capacitor integrators incur leakage errors and zero drift, hindering their accuracy. By contrast, spintronic devices with good scalability and endurance for memory and logic applications in digital circuits have yet to be studied for analog circuit elements. Here, we propose a single-device spintronic integrator based on the current-controlled magnetic domain wall (DW). Continuous DW motion and correlated changes in the anomalous Hall resistance (or magneto-resistance) are encoded as an analog output signal, which is modulated by an input current through the spin–orbit-torque effect. Waveform transformation and phase-shift functions are demonstrated using Hall-bar devices. The spintronic integrator could pave the way for the spin-based analog computing with high reliability, high endurance, and good compatibility with the CMOS process. [ABSTRACT FROM AUTHOR]

A wideband voltage-controlled oscillator (VCO) with coupling reduction and small VCO gain ( K v c o ) variation has been fabricated for multi-standard RF transceivers. A high-quality factor 8-shaped inductor is adopted to reduce the magnetic coupling between inductors and optimise the phase noise of the VCO. Electromagnetic simulations of magnetic coupling are carried out between an octagonal inductor and an 8-shaped inductor, and as high as 36 dB reduction in magnetic coupling is achieved by using 8-shaped inductors. A novel varactor group is proposed to realise a constant K v c o in the fine-tuning process, in which the scheme adopts an inversion-mode MOS varactor to revise the capacitance variation of an accumulation-mode MOS varactor. Meanwhile, an extra 3-bit varactor array is employed to reduce K v c o variation in the coarse tuning process. Based on a conventional TSMC 0.18-μm CMOS process, a nearly constant K v c o of 58 MHz/V is obtained for a wide frequency range of 4.02 to 5.48 GHz. The proposed VCO achieves a phase noise of less than −119.8 dBc/Hz at 1 MHz offset. The current consumption is 4.3–8.8 mA under a source voltage of 1.8 V. [ABSTRACT FROM AUTHOR]

In the quest for novel, scalable and energy-efficient computing technologies, spin-based logic devices are being extensively explored due to their potential for nonvolatility, small cell area, and low operational power. Spin torque majority gate (STMG) is one of the most promising options for beyond CMOS nonvolatile logic circuits for normally-off computing. However, significant problems arose with cascade-ability, signal nonreciprocity, and complicated circuit configurations based on STMG. In this paper, a novel magnetic majority gate (MMG) logic has been proposed, utilizing both spin transfer torque and spin–orbit torque effects. A logic family including and/nand and or/nor functions can be achieved with an easy configuration and under a stable operation. Communication between logic units is realized by spin current injection through a nonferromagnetic metal wire to ensure its cascade-ability and nonreciprocity to design multiple logic-depth circuits. With all of these advantages, the proposed cascadable MMGs can be utilized to design logic functions such as the BUFFER/ NOT, XOR/ XNOR, and complicated logic gates, which pave the pathway for designing robust and comprehensive logic circuits using full spintronic devices. [ABSTRACT FROM AUTHOR]

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id–Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current. [ABSTRACT FROM AUTHOR]

For boost power converter with Sensorless Current Mode (SCM) control, the inductor current is acquired by current estimator instead of current sensing. Without consideration of parasitics, the estimator is low-accurate, which affects system Small Signal Model (SSM) and degrades the control performance. In this paper, the issue is studied in frequency domain, and solved by a Corrective Frequency Compensation for Parasitics (CFCP) strategy. First, transfer functions for power converter, current estimator and current mode controller are given for frequency-domain analysis. Second, without consideration of parasitics, conventional proportional integral compensation is used to improve the system stability. Furthermore, with consideration of parasitics, converter main pole is replaced by two poles while a zero emerges at the origin. In order to cancel out the influence, the proposed CFCP strategy adopts a second-order transfer function to correct zero/pole variation induced by parasitics. Finally, steady state performance and transient response of the converter are improved, which are verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

The length of Source/Drain (S/D) extension ( L ) of nano-node p-channel FinFETs ( pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer L pFinFET provides a larger series resistance and degrades the drive current ( I ), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter L plus the shorter channel length demonstrates a higher trans-conductance ( G ) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer L represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current. [ABSTRACT FROM AUTHOR]

Exploring high-performance controller for buck converter is challenging since it can be easily affected by converter model accuracy. In this paper, a novel nonaveraged current discrete-time (NCD) model is proposed, in which inductor current is expressed as time-varying equations during switch-on and switch-off states. It achieves higher accuracy than the conventional averaged model at high-frequency range, thus can be used to optimize high-speed controller design. Based on the NCD model, a multiloop minimum switching cycle (MMSC) control strategy, composed of output feedback (OF), line feed forward (LFF), and reference feed forward (RFF) loops, is proposed and tuned for buck converter operating in continuous conduction mode. Mutual influences among three loops are considered and eliminated by specifically designed LFF and RFF compensations, which adapt the OF compensation. With consideration of sampling and calculation delays, relationship between transient switching cycles and geometric center of controller poles is discovered from a calculated output voltage error series. Furthermore, theoretical minimum switching cycles are calculated by moving the center inside the unit cycle of complex plane, which ensures system stability. Moreover, load/line transient response and reference tracking time are simultaneously optimized to the minimum switching cycles. Effectiveness of the controller is proved by converter closed-loop pole/zero plots, transient response simulations, and experiments. [ABSTRACT FROM AUTHOR]

A definite linear algorithm based on the constraint least squares solution for the structural equation model (SEM) is proposed. First, the modular constraint least squares solution is obtained. Then, the prescription constraint (the weight coefficients are non negative and their sum is one) is added, and the last solution of SEM is obtained. This definite linear algorithm is a new and reasonable algorithm compared to traditional algorithms like linear structural relationship (LISREL) and partial least squares (PLS). Finally, the application of SEM with the definite linear algorithm in fire risk evaluation is addressed, and the data example is calculated using software Data Analysis and Statistical Computation (DASC). [ABSTRACT FROM AUTHOR]

For discontinuous conduction mode (DCM) dc–dc converters with digital sensorless current mode (DSCM) control, an observed current error occurs, owing to a low-accuracy current observer. Moreover, a reference current error occurs due to a low-accuracy current controller or a finite dc gain of current loop. Conventionally, the observed current is compensated to increase current regulation accuracy, whereas the reference current error is neglected. However, for charge balance principle (CBP)-based DSCM (CBP-DSCM) control, this paper proves that the reference current should be compensated in a same quantity to that of observed current. Otherwise, single or unequal compensation leads to output voltage steady-state error. For this reason, a dual current error compensation strategy for CBP-DSCM control is proposed. It compensates the errors in a same quantity through a current error observer, which considers parasitics and calculates the current errors without approximation. To verify the proposed strategy, small-signal models with parasitics for both the converter and the controller are constructed by differential functions of key variables. Furthermore, converter stability is analyzed at typical operation condition, while the stability at various operation conditions is verified through robustness analysis. Finally, simulations and experimental results verify the analysis and the improved transient response of the converter. [ABSTRACT FROM AUTHOR]

Nowadays, deep learning algorithm has been widely used for automatic electrocardiogram (ECG) classification. However, most algorithms can only classify single heartbeat, which requires complex heartbeat extraction preprocessing. In addition, the traditional software implementation on CPU or GPU platform faces the challenge of low computing efficiency and high resource consumption. In this work, a deep one-dimensional (1D) U-net is proposed, which can classify the original continuous ECG segment at the pixel level. And an efficient hardware architecture is presented to implement the 1D U-net. A two-stage pipeline Winograd structure is designed to increase computing efficiency. A 3D processing element (PE) array is developed to improve resource utilization and overall throughput. Implemented on Xilinx Zynq ZC706 board, experimental results show that the proposed 1D U-net achieves an average accuracy of 95.55% for the pixel-level classification of five heartbeats. In terms of hardware performance, resource efficiency and computing efficiency reach 8.27 GOPS/kLUT and 123% respectively at 200 MHz clock frequency. [ABSTRACT FROM AUTHOR]

A dual-modulus prescaler (divide-by-2/3) using complementary clocking NMOS-like blocks is presented in this paper. The prescaler can work properly for both differential and single phase input clocks. For differential input clocks, the prescaler achieves not only high operating frequency but also low power consumption since it consists of only five NMOS-like blocks. For single phase input clock, the operating frequency range is further expanded by utilizing a complementary clocks generator. Simulation results show that, in 180-nm standard CMOS technology, the proposed prescaler achieves operating frequency range of 1.7-9.0 GHz for differential input clocks and 0.5-10.2 GHz for single phase input clock. And the maximum power consumption from 1.8 V power supply is 0.92 mW and 1.32 mW for differential and single phase input clocks respectively. [ABSTRACT FROM AUTHOR]

The extremely constrained resource has hindered the efforts to implement the elliptic curve cryptography (ECC) into a radio-frequency identification (RFID) tag chip. In this paper, an ECC-based RFID digital baseband controller (DBC), which is compatible with ISO/IEC 14443 and Schnorr authentication protocol, is presented. In order to achieve low resources consumption and fast ECC computation speed, some techniques, such as the register reuse, clock multiplexer, and asynchronous counter, are adopted in this design. In addition, a linear feedback shift register-based stream encryption scenario is proposed for the data security. According to the synthesis result, the gate area and power consumption of DBC are 25.7 K and 14.7 \mu\W, respectively, in UMC 0.13 \mu\m CMOS technology. All of those characteristics make the realization of ECC-based DBC for RFID tag chip promising. [ABSTRACT FROM PUBLISHER]

A high-linearity CMOS power amplifier (PA) operating at 2.45 GHz for WLAN applications with adaptive bias and an integrated diode linearizer is presented. The PA adopts adaptive bias scheme to adjust the gate bias voltage of power transistors by tracking the output power of the first diver amplifier for efficiency enhancement. Diode-connected MOS transistor is used to compensate the nonlinearity of input capacitance ( C gs ) of power transistors for linearity improvement. The simulation results demonstrate a gain of 33.2 dB, a maximum output power of 30.7 dB m with 29% of peak power added efficiency (PAE) and −30 dBc third-order intermodulation (IMD3) product at 26.4 dB m output power, reaching to excellent tradeoffs between efficiency and linearity. [ABSTRACT FROM AUTHOR]

For a sensorless predictive current controlled boost dc–dc converter, its small-signal model that contains a number of parasitic parameters, is derived in this paper. This model indicates that the type of system becomes type 0 even with the correction of voltage loop proportional–integral controller, leading to the existence of output voltage steady-state error. Then a self-correction differential current observer (SDCO) is proposed to eliminate this steady-state error and gain high transient response speed. The self-correction part of the SDCO makes the system become type 1 to achieve no steady-state error for output voltage, whereas the differential part can guarantee that the intermediate calculation results do not overflow. By carrying out a series of simulation verifications, further investigation proves that the proposed algorithm has good robustness. Finally, the effectiveness of the proposed algorithm is verified by experimental results. [ABSTRACT FROM PUBLISHER]

A novel wideband down‐conversion mixer is proposed for multi‐standard wireless applications between 100 MHz and 2.5 GHz. A transconductance stage with two pairs of compensatory transistors is adopted for high linearity. Differing from the ordinary differential multi‐gated transistor technique utilised in Gilbert mixer, the design proposed concerns about both gm″ and gm compensation of the transconductance stage in order to improve both input‐referred third‐order intercept point (IIP3) and 1 dB gain compression point (CP1 dB). Realising in Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm RF CMOS process, the mixer provides a gain of 8.9 dB, a maximum IIP3 of 5.8 dBm, a maximum CP1 dB of −4 dBm and a minimum noise figure (NF) of 9.6 dB. [ABSTRACT FROM AUTHOR]

A high‐linearity CMOS power amplifier (PA) operating at 2.4 GHz with an integrated diode lineariser is presented. A diode‐connected N‐type MOS transistor is used to increase the Vgs of the power transistor as input power increases for linearity improvement. The CMOS PA fabricated in 180 nm CMOS technology achieved 32 dB small signal gain, 30.2 dBm Psat, 28.2 dBm P1 dB, and a 31.1% peak power added efficiency. By adopting the proposed diode lineariser, the output 1 dB is improved from 24.9 to 28.2 dBm. [ABSTRACT FROM AUTHOR]

This paper presents an accurate ISF-based phase noise analysis method for LC/Ring oscillators. The proposed method can simultaneously quantify the effect of flicker noise and thermal noise on phase noise. The impulse sensitivity function (ISF) tool is used to evaluate the effect of flicker noise sources. An equivalent thermal noise resistor is utilized to assess the thermal noise contribution and simplify the analysis process. Based on the proposed method, the phase noise performance of a voltage-controlled oscillator (VCO) with source damping resistors is discussed. Simulated in 180-nm TSMC and 110-nm HHGRACE CMOS processes, the accuracy of the proposed method is verified. The predicted phase noise performance is consistent with the simulation results in 1/ f 3 and 1/ f 2 region, achieving 1-dB accuracy in diverse oscillator topologies. [ABSTRACT FROM AUTHOR]

A wideband voltage‐controlled oscillator (VCO) covering 2.24–4.95 GHz for multi‐standard wireless applications is presented. Realised in TSMC 180 nm RFCMOS process, the VCO provides a phase noise <–124.2 dBc/Hz at a 1 MHz offset in the whole frequency range, while drawing 10 and 18 mA at 4.95and 2.24 GHz from a 1.8 V supply, respectively. The achieved tuning range is 75% and the core chip area is 0.51 mm². [ABSTRACT FROM AUTHOR]

A wideband single‐ended input, differential output balun‐LNA is proposed for multi‐standard wireless applications between 10 MHz and 3 GHz. The common‐gate (CG) input stage in combination with a noise cancellation topology is adopted for wideband input matching and low‐noise figure. An output stage with gm″ compensation technique is utilised to promote the limited gain of the CG input stage, and obtain an optimised linearity performance. Realised in TSMC 180 nm RF CMOS process, the LNA provides a gain of 19.7 dB, a maximum input third‐order interception point of 1.13 dBm, and a minimum NF AQ1 of 1.93 dB over a 3 dB bandwidth from 10 MHz to 1.7 GHz. Meanwhile, the proposed LNA shows good measured performance over the frequency band of 1.7–3 GHz. [ABSTRACT FROM AUTHOR]

An enhanced electrostatic discharge (ESD) power clamp for an antenna switch controller with silicon‐on‐insulator (SOI) complementary metal‐oxide‐semiconductor (CMOS) technology is presented. The gate drive voltages of larger n‐type metal‐oxide‐semiconductor transistors in a stacked configuration of a RC‐triggered power clamp have been optimised to obtain larger discharging capability and shorter turn‐on time compared to the conventional topology. The proposed ESD power clamp circuits are implemented in a double‐pole five‐throw antenna switch controller and the experimental results confirm the validity of this approach. [ABSTRACT FROM AUTHOR]