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Three dimensional Networks-on-Chip (3D NoCs) have evolved as an ideal solution to the communication demands and complexity of future high density many core architectures. However, the design practicality of 3D NoCs faces several challenges such as thermal issues, high power consumption and area overhead of 3D routers as well as high complexity and cost of vertical link implementation. To mitigate the performance and manufacturing cost of 3D NoCs, inhomogeneous architectures have emerged to combine 2D and 3D routers in 3D NoCs producing lower area and energy consumption while maintaining the performance of homogeneous 3D NoCs. Due to the limited number of vertical links, application mapping on inhomogeneous 3D NoCs can be complex. However, application mapping has a great impact on the performance and energy consumption of NoCs. This paper presents an energy and performance aware application mapping algorithm for inhomogeneous 3D NoCs. The algorithm has been evaluated with various realistic traffic patterns and compared with existing mapping algorithms. Experimental results show NoCs mapped with the proposed algorithm have lower energy consumption and significant reduction in packet delays compared to the existing algorithms and comparable average packet latency with Branch-and-Bound. [ABSTRACT FROM AUTHOR]

Efficient on-chip communication is necessary for exploiting enormous computing power available on a many-core chip. Routing algorithms play a major role for the communication quality and performance of the on-chip interconnection networks. This paper proposes TagNoC, as an on-chip network router architecture with novel hybrid routing approach which reduces latency and power consumption at a fixed cost based on information redundancy. TagNoC is a hybrid routing approach which combines the source and distributed routing methods together. While eliminating packet routing in each router, TagNoC determines the forwarding output port in parallel with input buffering. For a marginal cost increase in header size, as compared to distributed routing techniques, routing latency can be hidden while eliminating power consuming portion of the routing, increasing router throughput and decreasing latency. The proposed TagNoC router is compared to baseline router with distributed routing implementation on a 16-node CMP mesh. Physical implementation of all routers is modeled using synthesized RTL, detailed area analysis, and accurate channel models. Performance evaluation is also carried out utilizing RTL simulation and detailed power analysis on both synthetic and application traffic is performed using post-synthesis gate-level simulation. The simulation results illustrate that TagNoC outperforms as compared to baseline distributed architecture and other source routing methods in terms of power, latency, and throughput. [ABSTRACT FROM AUTHOR]

Abstract: Integration of hundreds of processors on a chip will become practical thanks to ultra-deep submicron VLSI technology. As wiring delay becomes a bottleneck for a scalable design, on-chip interconnects turn into the critical issues for system performance and reliability. To mitigate long wiring delay impact, wireless on-chip communication infrastructures featuring hybrid mechanisms exploiting both wired and wireless communications have been proposed. By shortening long distance transmission latency and lowering wired network overhead, overall system transfer latency and energy dissipation are improved accordingly. However, unbalanced traffic management reduces the benefit of high speed wireless links so that wired networks also degrade accordingly. To extract the best performance for these hybrid networks, an intelligent congestion-aware router design is needed to balance traffic load and eliminate congestion delay. A sophisticated routing scheme accommodating more throughput and featuring light weight congestion-aware mechanism which uses the number of blocking buffers as a guideline to avoid serious congestion was designed and evaluated. Modified 7-port routers achieve better performance and the proposed routing algorithm successfully eliminates congestion scenarios and efficiently balances traffic loads. This is the first work to exchange congestion information locally and globally to improve network utilization and transmission quality. The experimental results showed significant improvement in transfer latency, network throughput and power efficiency with moderate hardware cost overhead. [Copyright &y& Elsevier]

In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs, such as having same mobility for electrons and holes and also capability of adopting desirable threshold voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise margins and higher robustness as compared to the previous CNTFET-based designs. The proposed quaternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42% and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) exhibits a new paradigm at nanoscale for possible substitution of conventional CMOS technology. Most of the research works in QCA domain have completely ignored the significance of energy consumption constraint in designing circuits. In this study a low complexity and energy-efficient QCA T flip–flip as well as high-performance single-layer synchronous counters are proposed. By cascading the proposed T flip-flop and a suitable level converter, a QCA-compatible structure for falling edge triggered T flip-flop is achieved. This circuit functions as the chief element for constructing synchronous counters. QCADesigner and QCAPro tools are used for evaluating the functionality and calculating dissipated energy of the circuits, respectively. Results indicate the superiority of the proposed circuits in terms of complexity, latency and energy consumption as compared to their state-of-the-art counterparts. The proposed T flip-flop demonstrates 18% leakage energy improvement besides the considerable value of 56% switching energy improvement in 0.5Ek tunneling energy level as compared to the best ones. It is worth mentioning that 41%, 44% and 45% optimizations in the number of cells in addition to 15%, 25% and 33% optimizations in the area are achieved for the proposed mod 4, mod 8 and mod 16 counters, respectively, in comparison with the best previous results. [ABSTRACT FROM AUTHOR]

Abstract: 3-D Networks-on-Chip (NoCs) have been proposed as a potent solution to address both the interconnection and design complexity problems facing future System-on-Chip (SoC) designs. In this paper, two topology-aware multicast routing algorithms, Multicasting XYZ (MXYZ) and Alternative XYZ (AL+XYZ) algorithms in supporting of 3-D NoC are proposed. In essence, MXYZ is a simple dimension order multicast routing algorithm that targets 3-D NoC systems built upon regular topologies. To support multicast routing in irregular regions, AL+XYZ can be applied, where an alternative output channel is sought to forward/replicate the packets whenever the output channel determined by MXYZ is not available. To evaluate the performance of MXYZ and AL+XYZ, extensive experiments have been conducted by comparing MXYZ and AL+XYZ against a path-based multicast routing algorithm and an irregular region oriented multiple unicast routing algorithm, respectively. The experimental results confirm that the proposed MXYZ and AL+XYZ schemes, respectively, have lower latency and power consumption than the other two routing algorithms, meriting the two proposed algorithms to be more suitable for supporting multicasting in 3-D NoC systems. In addition, the hardware implementation cost of AL+XYZ is shown to be quite modest. [Copyright &y& Elsevier]

Abstract: This paper proposes a novel Network-on-Chip architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also provides a power-efficient solution for interconnection network scenarios. Diagonally-linked mesh NoC that uses wormhole packet switching technique implements a high-performance NoC platform to meet both cost and power consumption requirements. The proposed architecture uses an adaptive quasi-minimal routing algorithm so that it can improve average latency and saturation traffic load owing to its flexibility and adaptiveness. Based on these features, a congestion-aware routing algorithm is proposed to balance traffic load so as to alleviate congestion caused by high throughput network activities. Simulation results show that saturation load is improved dramatically for various traffic patterns. Implementation results also show that employing diagonal links is a more area-efficient method for improving network performance than using large buffers. It is shown that congestion-aware router requires negligible cost overhead but provides better throughput. Finally, simulation results also reveal that power consumption in the proposed architecture outperforms traditional mesh networks. [Copyright &y& Elsevier]