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This paper deals with a low-cost method for the assembly of flexible substrate antennas and UHF RF identification silicon (Si) chips. Such a method exploits a magnetic coupling mechanism, thus not requiring for galvanic contacts between the Si chip and antenna itself. The magnetic coupling is established by a planar transformer, the primary and secondary windings of which are implemented on flexible substrate and Si chip, respectively. As a result, the Si chip can be assembled on the antenna with a mere placing and gluing process. First, the idea has been validated by theory. Electromagnetic simulations of a square heterogeneous transformer (1.0-mm side) show a maximum available power gain (MAG) of -0.4 dB at 868 MHz. In addition, the heterogeneous transformer is also quite tolerant with respect to misalignment between primary and secondary. An offset error of 150 \mu\ m reduces the MAG to -0.5 dB. A sub-optimal matching strategy, exploiting a simple on-chip capacitor, is then developed for antennas with 50-\Omega input impedances. Finally, the idea has been experimentally validated exploiting printed circuit board (PCB) prototypes. A PCB transformer (1.5-mm side) and a transformer rectifier (two-diode Dickson multiplier) have been fabricated and tested. Measurements indicates a MAG of -0.3 dB at 868 MHz for the transformer and the capability of the developed rectifier to supply a 220-\k\Omega load at 1.5 V with a -2-dBm input power. [ABSTRACT FROM AUTHOR]

Two challenges are combined when compressed tests are computed for path delay faults: 1) path delay faults that are important to detect are associated with long paths, and many of these faults are undetectable and 2) it may not be possible to compress a given test for a path delay fault. This paper addresses these challenges in the context of test data compression methods that are based on a linear-feedback shift-register (LFSR). The basic approach that this paper uses modifies initially random seeds for the LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in this paper also selects detectable path delay faults to address the presence of undetectable path delay faults in the set of target faults. For this purpose it uses a metric that measures the similarity between target and detected path delay faults, and attempts to compute seeds that increase the values of this metric. Experimental results are presented to demonstrate the ability of the procedure to detect path delay faults in benchmark circuits. [ABSTRACT FROM AUTHOR]

The operation of static random access memory (SRAM) in the subthreshold region reduces both leakage power and access energy. Subthreshold operation is one of the proficient techniques to accomplish low-power and high performance system on chip. But the challenge, in subthreshold SRAM design, is the SRAM stability. The sensitivity to process variations increases with technology scaling resulting in reduced stability. In this paper, SRAM write stability is analyzed in the subthreshold region. The semi-analytical model of write static noise margin (WSNM) for 6T SRAM (subthreshold region) has been given in this paper. The results obtained from the analytical model are verified through simulations in Cadence using GPDK 45-nm, UMC 65-nm, and UMC 130-nm technology files. The model is based on the subthreshold current equations of the transistor. Further, the write stability of the SRAM is analyzed with the varying supply voltage and the sizing ratios. The process corner analyses is also accomplished to verify the write stability of the SRAM cell using the model at the worst process corners. To the best of the author’s knowledge, this is the first model to analyze the WSNM based on the traditional butterfly static noise margin approach. It has been observed that the model is valid for all of the technology nodes, i.e., at 45 nm, 65 nm, as well as 130 nm. Also the model holds well for 8T and 10T SRAM configurations in addition to 6T SRAM cell. [ABSTRACT FROM PUBLISHER]

Cascaded H-bridge (CHB) is a promising topology for medium-voltage high-power applications. CHB consists of low-power H-bridge modules in each phase, and these modules are connected in a cascade manner to achieve multilevel operation. However, CHB requires a phase-shifting transformer with multiple secondary windings to generate an isolated dc source for each module, and this requirement increases the overall system cost. In this paper, a series connection of low-power modules is employed to realize a new power converter called a series-connected multilevel converter. Each phase of the proposed topology requires a single isolated dc source. Hence, the required number of secondary windings is considerably reduced. This approach also minimizes the complexity and cost of the overall system. The operation of the proposed topology is presented by using three-level neutral point clamped modules in each phase. Model predictive control (MPC) is employed to control the dc-bus capacitor voltage and output currents of the proposed topology. A discrete-time mathematical model of the proposed topology is also developed to predict the future behavior of control variables. The performance of the proposed topology with MPC is verified through MATLAB simulations and a scaled-down laboratory prototype. [ABSTRACT FROM AUTHOR]

In past studies on cascading failure assessment, the risk of N – x initiating contingencies (ICs) regarding their initiating effect and hidden contingency risk (a high-risk x-component outage sequence within the IC) may not be fully investigated, which may underestimate the risk of IC-triggered cascading overload failures (COFs). In addition, the research on the efficient screening of N – x IC (x ≥ 2) and the identification of the cascading with the largest system impact is limited. To undertake this challenge, this paper proposes a COF identification approach (CIA) which integrates the IC screening and the COF identification for finding the high-impact COFs initiated by N – x ICs with hidden risks. The CIA is validated by simulations on the IEEE 118-bus system. The simulation results demonstrate that the CIA can efficiently screen out the high-risk N – 2 and N – 3 ICs that have an optimal outage sequence and trigger COF chains. The results also show that the CIA can identify the IC-triggered high-impact COFs and quantifies their impacts. The approach can be used as either a cascade-triggering event screening tool (by applying the IC screening module) or a COF risk assessment tool for ensuring system reliability. [ABSTRACT FROM AUTHOR]

Network-on-chip (NoC) mapping algorithms significantly affect NoC system performance in terms of communication cost and energy consumption. For a specific application represented by a task graph, this paper proposes an energy-efficient mapping algorithm that searches for the mapping decision with best communication locality and therefore lowest energy consumption. To this end, we formulate the concerned mapping problem as an optimization model, and propose an effective meta-heuristic algorithm to solve the formulated optimization model. During the mapping procedure, we employ a simulation-free, communication probability-based energy model to evaluate the quality of each candidate mapping. By iteratively updating the best explored mapping decision using a meta-heuristic search strategy, the mapping procedure can eventually identify an mapping decision with optimal energy efficiency in the search space. The proposed mapping algorithm has been verified on NoC systems of different sizes using a variety of benchmark applications. Simulation results demonstrate that the mapping decision produced by this algorithm achieves an up to 23% energy reduction compared with the traditional round-robin strategy. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

In some application circumstances, both positive and negative sequence reactive power compensations are desired from the star-connected cascaded H-bridge static synchronous compensator (CHB STATCOM). However, the imbalanced phase currents/voltages will cause uneven active power flow among three clusters, which makes the cluster voltage balance more challenging. In this scenario, only zero sequence voltage is available to balance the cluster voltages. Although the zero sequence voltage can be calculated in all operating conditions based on the equilibrium of the active power for each phase cluster, the calculation is definitely complicated due to the zero sequence voltage expressed in the form of trigonometric function in the abc or dq0 frame. In this paper, the zero sequence voltage is represented in a dc form in the dq frame through introducing a virtually orthogonal zero sequence voltage. As a result, a linear relationship between the active powers and the zero sequence voltage is established, based on which, a simple zero sequence voltage calculation method is proposed with a small calculation burden. Furthermore, the accurate compensation region for the negative sequence current injection is identified by establishing the relationship between the maximum converter voltage and the negative sequence currents taking into consideration the initial phase angle of the negative sequence currents, while still keeping the cluster voltage balanced by using the zero sequence voltage control. The effectiveness of the proposed control and the compensation region are verified by the simulation and experimental results on a 400 V/±7.5 kVAr star-connected CHB STATCOM. [ABSTRACT FROM AUTHOR]

This paper proposes a direct space-vector modulation (DSVM) method that can reduce the common-mode voltage (CMV) as well as the switching losses for matrix converters in a high voltage transfer ratio. Even though the previous DSVM improvements can reduce the CMV peak value to 42%, compared to the conventional DSVM method, they incur high switching losses. The DSVM method proposed in this paper provides the same CMV peak value as previous methods with lower switching losses. The switching losses are theoretically analyzed through the accumulated switched voltage in a switching period and compared to those of previous methods. Simulation and experimental results are given to verify the input/output waveforms, CMV reduction, and lower switching losses of the proposed DSVM method. [ABSTRACT FROM AUTHOR]

Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumption, and performance. Simulations are computationally expensive making it rather hard to efficiently explore the design space to identify high-quality configurations in an acceptable exploration time when relying solely on a single-core machine to run simulations. To tackle this problem, engineers proposed solutions based on either: 1) the use of approximate analytic performance models to prune the suboptimal regions of the design space by reducing the number of simulations to run or 2) the use of parallel computing resources to run different simulations concurrently. In this paper we demonstrate that, to efficiently speedup the DSE process while fully exploiting the parallel computing infrastructure, we need to combine the two techniques together in a structured manner. In this paper, we investigate this issue and we propose a DSE solution that exploits approximate analytic prediction models to improve the simulation schedule on a parallel computing environment rather than to prune the number of simulations. Experimental results demonstrate that the proposed technique provides a speedup from 1.26\boldsymbol \times to 4\boldsymbol \times with respect to other parallel state-of-the art DSE techniques. [ABSTRACT FROM PUBLISHER]

In this paper, the application of operational transconductance amplifier (OTA), in addition to comparing with the interior structures of the most important available integrated circuits, have been analyzed. In this regard, a model in Spice has been presented to facilitate the trend of education for the undergraduate based on OTA theoretical analysis. The present paper aims to offer a model for the OTA in Spice from which the theoretical features of the said amplifiers can be incorporated. This causes the application of the OTA integrated circuits, under the impression and contribution of computerized simulation, and the accuracy of the theoretical analyses to be instructed and to be studied respectively. At the end, to show the merit and competence of the proposed model, three practical circuits, whose results are compared to the theoretical values and simulation accuracy, are represented. The proposed model covers the high speed of simulation and appropriate numerical convergence. [ABSTRACT FROM AUTHOR]

This paper deals with the measurement methods used to evaluate the electromagnetic (EM) emission of integrated circuits (ICs) as well as their susceptibility to EM interference. In particular, the micro stripline method, which is prescribed by the International Electrotechnical Commission (IEC 62132-8), is considered and its limitations for the characterization of ICs encapsulated in small packages are highlighted. Wanting to address such issues, a new EM guiding structure that shows an enhanced coupling with the device under test in the frequency range 800 MHz–3 GHz is proposed. A circuit model of the test structure based on lumped elements that allows one to perform circuit analysis with SPICE-like simulators is proposed. It can also be used to check the effectiveness of the test bench before setting it up. The model has been validated comparing the scattering parameters obtained from simulations with those resulted from measurements carried out on a real test structure, which was designed and fabricated for this purpose. [ABSTRACT FROM PUBLISHER]

Near-threshold and sub-threshold voltage designs have been identified as possible solutions to overcome the limitations introduced by energy consumption in modern very large scale integration circuits. However, as we approach sub-10 nm transistor technology, aggressive voltage, and gate length scaling will reduce the reliability of logic circuits due to the increasing impact of noise and variability effects. Therefore, designers need new tools to simulate logic circuits in the presence of noise. Time-domain analysis helps understand how transient faults affect a circuit and can guide designers in producing noise-resistant circuitry. However, standard approaches to modeling intrinsic noise sources in the time domain are computationally expensive. Moreover, small noise-driven fluctuations in electron occupation of circuit nodes introduce time-varying biasing point fluctuations, increasing the modeling complexity. To address these challenges, this paper introduces a new approach to modeling thermal noise and random telegraph signal noise directly in the time domain by developing and solving a series of stochastic differential equations. In comparisons to traditional SPICE-based simulations, our approach can provide three orders of magnitude speedup in simulation time without sacrificing accuracy. Moreover, we introduce a novel, iterative threshold-crossing algorithm, aimed at the efficient sampling of rare noise transients. We show that Monte-Carlo simulations based on this approach can detect rare high-amplitude single event transients that would be impossible to uncover with standard transient simulators. [ABSTRACT FROM PUBLISHER]

This paper proposes novel mixed-mode S-parameters, which are dubbed as “extended mixed-mode S-parameters.” The extended mixed-mode S-parameters were applied to three-conductor transmission lines, resulting in the independent differential and common modes using the current division factor of three-conductor transmission lines. By contrast to the conventional mixed-mode S -parameters, there are no cross-mode S-parameters in the extended mixed-mode S -parameters, even in the asymmetrical conductor transmission lines. In addition, two new mode conversion matrices, which contain the current division factor, are also proposed to convert the extended mixed-mode S -parameters to the standard S-parameters. The validity of the proposed extended mixed-mode S -parameters and the mode conversion method were confirmed by comparing the S-parameters from the theory, EM-simulation, and experiment as well. [ABSTRACT FROM PUBLISHER]

In order to expand the simulation scale of smart substation, a simulation model of the inlet-outlet line unit, as described by the 0/108 S conductance for multivalued coefficients pre-storage is presented in this paper. As a part of orders decomposition, the address conversion circuit for multivalued coefficients can reduce the computational burden of processing elements. For the convenience of the generalization of the real-time digital solver based on FPGA (FRTDS, FPGA: Field-Programmable Gate Array), the address conversion circuit for multivalued coefficients is matched with the guide word, the formation module of sampled value (SV) packet, and the resolution module of generic object oriented substation event (GOOSE) packet are associated with the application identification (APPID) in the Ethernet frame. The address conversion circuit for multivalued coefficients, the formation module of SV packet, and the resolution module of GOOSE packet are reconstructed via the orders. A hardware-in-the-loop real-time simulation platform for smart substation is built based on the novel FRTDS. A case is given to demonstrate the simulation calculating capability and the hardware-in-the-loop ability of the novel FRTDS. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMC) have revolutionized the voltage-sourced converter-based high-voltage direct current transmission, but not yet got widespread application in medium-voltage variable-speed motor drives, because of the large capacitor voltage ripples at low motor speeds. In this paper, a novel hybrid MMC topology is introduced, which significantly reduces the voltage ripple of capacitors, particularly at low motor speeds. Moreover, this topology does not introduce any motor common-mode voltage; as a result, there are no insulation and bearing current problems. Additionally, the current stress can remain at rated value throughout the whole speed range; thus, no device needs to be oversized and converter efficiency can be ensured. Operating principle of this hybrid topology is explained, and control schemes are also developed. Validity and performance of the proposed topology are verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

In the case of partial shading, the output power of the unshaded PV modules will be decreased by the influence of the shaded PV modules in one branch. In order to solve this problem, this paper proposes a novel topology for a PV power generation system by connecting a PV module to the capacitor in each submodule of a modular multilevel converter parallel. As partial shading occurs, the maximum power can be extracted by regulating the capacitor voltage to the maximum power point voltage. With this proposed topology, the maximum power tracking controller, the redundancy module controller, the voltage stability controller, and the grid-connected controller are studied. Simulation and experiment results show that comparing to the traditional topology, the proposed topology can greatly improve the output power of the PV system under the conditions of partial shading and features with low-voltage stress and high efficiency. [ABSTRACT FROM AUTHOR]

With silicon technology further scaling, the switching activity is getting more intense in modern designs. The large switching activities together with GHz operation frequency can greatly affect the power integrity by generating IR-drop noises. Excessive IR-drop can cause functional failures such as timing failure, abnormal reset and SRAM flipping. Hence, IR-drop needs to be monitored in-field. However, directly measuring transient IR-drop waveform usually involves high design or equipment cost. This paper presents a low-cost on-chip GHz ring oscillator-based transient IR-drop monitor (TRO). TRO is composed of all-digital elements, and can be easily integrated into existing IC design flow with negligible overhead. Different from traditional transient IR-drop monitors, TRO measures IR-drop waveform width and average in-field, while recovers IR-drop peak, and reconstructs the transient noise waveform during data analysis or customer return, which eliminates the need for custom circuits or high frequency sampling clock. Simulation results show that TRO is sensitive to IR-drop with peak and width larger than 100 mV and 1.0 ns, which is suitable for GHz IC monitoring. The IR-drop noise width detection resolution can reach 0.125 ns and higher under the help of the proposed edge detector, with noise peak and width measurement error rate less than 6.8% and 9.0%, for 97% of the Monte Carlo samples considering process variations. According to the results and analyses, TRO is also able to trigger quick adaptation within one clock cycle. [ABSTRACT FROM AUTHOR]

Advances in digital microfluidic (DMF) technologies offer a promising platform for a variety of biochemical applications, ranging from massively parallel DNA analysis and computational drug discovery to toxicity monitoring and medical diagnosis. In this paper, we address the migration problem that arises when the technology undergoes a change in the context of DMFs. Given a biochemical reaction synthesized for actuation on a given DMF architecture, we discuss how the same biochemical reaction can be ported seamlessly to an enhanced architecture, with possible modifications to the architectural parameters (e.g., clock frequency, mixer size, and mixing time) or geometric changes (e.g., change in reservoir locations or mixer positions, inclusion of new sensors or other physical resources). Complete resynthesis of the protocol for the new architecture may often become either inefficient or even infeasible due to scalability, proprietary, security, or cost issues. We propose an adaptation method for handling such technology-changes by modifying the existing actuation sequence through an incremental procedure. The foundation of our method lies in symbolic encoding and satisfiability-solvers, enriched with pertinent graph-theoretic and geometric techniques. This enables us to generate functionally correct solutions for the new target architecture without necessitating a complete resynthesis step, thereby enabling the utilization of these chips by users in biology who are not familiar with the on-chip synthesis tool-flow. We highlight the benefits of the proposed approach through extensive simulations on assay benchmarks. [ABSTRACT FROM AUTHOR]

By the logical statements and linear inequalities, a new modeling method named bi-switching status modeling (BSM) method is presented to model the dc–dc converters in this paper. Compared with other modeling methods, such as the state-space averaging method and the mixed logical dynamical (MLD) method, first, the BSM method can describe continuous conduction mode and discontinuous conduction mode operations of the dc–dc converters as a unified bi-switching status model. Second, the BSM method is more precise than the state-space averaging method because there is no approximate assumption. Third, the constrains of the operating modes in the BSM method can be simplified as a consolidated inequality, which means that the model obtained by the BSM method is more concise than that obtained by the MLD method. Simulation and available experiments of a buck converter verify the effectiveness of the proposed BSM method. [ABSTRACT FROM PUBLISHER]

This paper focuses on the modelling and control of an interline current flow controller (CFC) for meshed HVDC grids. The operation states of the CFC are presented, and an average model is derived. The average model is used to perform steady-state analysis on a 3-terminal meshed grid, showing the current change capabilities and the benefits on the operation area. The converter control is designed using a linearized model. The system performance of the CFC is tested by means of simulation in a 3-terminal grid and in a 5-terminal grid. [ABSTRACT FROM AUTHOR]

This paper analyzes the effect of digital differentiation on the measurement of flicker emission from grid-connected wind turbines (WTs). The flicker measurement procedure is defined in the IEC 61400-21 standard, which includes the estimation of a fictitious grid for the measurement of voltage fluctuations exclusively generated by a WT. The study focuses on two aspects of the implementation of the derivative of the line current that affect the estimation of the fictitious grid, namely the bandwidth and the phase response of the digital differentiator. The experiments were performed under two different frameworks, by using simulated simple waveforms and voltage and current recordings from an actual WT. The work cautions about the adverse effect of the phase response of the even-length finite impulse-response differentiators. It also recommends implementing digital differentiators with an accurate bandwidth to derive potential spectral components in the current in the whole bandwidth required by the procedure. This aim can be achieved by increasing either the length of the filter or the sampling rate of the processing. The conclusions should help in accurately implementing the procedure and reducing the deviations found in the flicker emission measurements for grid-connected WTs. [ABSTRACT FROM AUTHOR]

In this paper, an X-tolerant multiple-input signature register (MISR) compaction methodology that compacts output responses containing unknown X values is described. Each bit of the MISR signature is expressed as a linear combination in terms of Xs by symbolic simulation. Linearly dependent combinations of the signature bits are identified with Gaussian elimination and xored to remove X values and yield deterministic values. Two X-canceling MISR architectures are proposed and analyzed with industrial designs. This paper also shows the correlation between the estimated result based on idealized modeling and the actual data for real circuits for error coverage, hardware overhead, and other metrics. Experimental results indicate that high error coverage can be achieved with X-canceling MISR configurations and it highly correlates with actual results. [ABSTRACT FROM AUTHOR]

Multiplayer games are played by a set of agents, where, at each round, all players give their moves, and the combination of their moves defines the successor states for the game. In such games, the players pursue certain goals with their moves and in that pursuit, they can form coalitions to fulfill a common objective. In this paper, we adopt this model of multiplayer coalition games in the context of 3-party systems, consisting of a module, its environment, and a controller. The winning objective of our game is given as a specification in linear temporal logic and the module and controller together attempt to satisfy the specification for all possible strategies of the environment. In this paper, we analyze the problem for various degrees of observability of the module–controller pair, and provide quantified Boolean formula-based methods for investigating the existence of a winning coalition strategy. The coalition strategy can only be fulfilled on carefully implementing both the module and the controller such that they can cooperate. We also consider the problem where the implementations of the module and the controller are available and we present a dynamic simulation-based approach for verifying whether these implementations conform to the coalition requirements. In case, they do not, we provide algorithms for designing the winning strategy for an intelligent environment to drive the coalition to a refutation. [ABSTRACT FROM AUTHOR]

Motivated by the promising benefits of dynamic time division duplex (TDD), in this paper, we use a unified framework to investigate both the technical issues of applying dynamic TDD in homogeneous small-cell networks (HomSCNs) and the feasibility of introducing dynamic TDD into heterogeneous networks (HetNets). First, HomSCNs are analyzed, and a small-cell base-station (BS) scheduler that dynamically and independently schedules downlink (DL) and uplink (UL) subframes is presented, such that load balancing between the DL and UL traffic can be achieved. Moreover, the effectiveness of various interlink interference mitigation (ILIM) schemes and their combinations is systematically investigated and compared. Moreover, the interesting possibility of partial interference cancelation (IC) is also explored. Second, based on the proposed schemes, the joint operation of dynamic TDD together with cell range expansion (CRE) and almost blank subframe (ABS) in HetNets is studied. In this regard, scheduling polices in small cells and an algorithm to derive the appropriate macrocell traffic offload and ABS duty cycle under dynamic TDD operation are proposed. Moreover, the full IC and the partial IC schemes are investigated for dynamic TDD in HetNets. The user-equipment (UE) packet throughput performance of the proposed/discussed schemes is benchmarked using system-level simulations. [ABSTRACT FROM AUTHOR]

In practical printed circuit board (PCB) designs, electromagnetic interference (EMI) is coupled from the ground plane, which is commonly shared among the analog, digital, and mixed-signal integrated circuits. This noisy ground plane couples interference capacitively to all the IC pins, including the output: this effect is exacerbated when the IC is connected to long wires and traces that are routed close to the conductive ground plane. This paper reports on the effect of interference, which is coupled capacitively from the PCB ground plane into all the IC pins of an opamp connected as a voltage buffer. Simulations illustrate the susceptibilities in custom operational amplifier designs, and are corroborated by measurements on several commercial devices. These measurements show that the EMI-induced offset can attain considerable values for the most critical EMI frequencies, which lie between 10 and 100 MHz. Moreover, these illustrate that there is a considerable susceptibility of operational amplifiers to electromagnetic interference coupled to their output pins. [ABSTRACT FROM AUTHOR]

This paper presents a new diagnostic technique for the diagnosis of open-circuit faults in matrix converters operating with an Optimum Alesina-Venturini modulation scheme. Compared to previous diagnostic techniques developed for matrix converters, the technique proposed in this paper has the major advantage of not requiring the installation of any additional sensors in the converter besides the ones already present for control purposes. Hence, it can be easily integrated into the control platform of the converter at no additional cost. In addition to the diagnostic approach, a new fault-tolerant switching strategy is also presented so that after the appearance of an open-circuit fault, the matrix converter can continue to run although with degraded performance, until a repair action can be taken. Several simulation and experimental results are presented, demonstrating the effectiveness and applicability of the developed techniques. [ABSTRACT FROM AUTHOR]

This paper investigates the buck–boost dc–dc converter and the energy transmission techniques in this kind of converter. In this paper, the critical inductance between the continuous conduction and discontinuous conduction modes are determined. In addition, the critical inductance equation between the complete inductor supply mode and incomplete inductor supply mode are calculated. The energy transmission technique and the output voltage ripple (OVR) of a buck–boost converter are analyzed in a specific range of the load and input voltage. The relations between the maximum OVR (MOVR) and the converter component parameters are deduced, and the minimum inductance value is calculated to ensure the MOVR minimization. Experimental and simulation results are used to prove the validity of the presented theoretical subjects. [ABSTRACT FROM AUTHOR]

Applying the Jiles-Atherton (JA) model to simulate the dynamics of power electronics circuit is a challenge but very attractive since it is possible to carry out continuous simulation with only several input parameters. Although other methods such as the Preisach-model can result in approximate waveforms for such applications, it is still a far distance to reach exact ones to suit chaos and other high accuracy-requiring researches. In this paper, the JA model has been successfully applied to model the dynamics of resonant inverter for driving a nonlinear load: a fluorescent lamp. The circuit is driven by a high frequency square wave voltage source. A semi-theoretical fluorescent lamp model developed from HID lamp model is adopted in the modeling. The simulation waveforms of voltage across the lamp and current through it are close to those measured ones reported in the literature papers. [ABSTRACT FROM AUTHOR]

With a direct integration of a field effect transistor (FET) into a C-shaped ring radiator, a novel miniaturized self-oscillating annular ring active integrated antenna is proposed and investigated in this paper. The direct integration approach provides a solid basis for the miniaturization while the slow-wave loading effect from the unstable transistor further enhances the reduction ratio. It makes the proposed design show an extraordinarily compact size of 0.041\lambdag^{2}, which is 40% the size of the second smallest one in literature using printed circuit board technology. The proposed active antenna, providing overall comparable performance to the previous designs, has an EIRP of 7.30 dBm, DC-to-RF efficiency of 25.9%, phase noise of -91.9 dBc/Hz@100 kHz offset, and an oscillator FOM of -168.76 dBc/Hz. By introducing a reverse-biased varactor diode, this miniaturized active antenna also demonstrates promising voltage controllability with a high VCO gain of 48.7 MHz/V. The antenna geometry and modeling, design concept, simulation scheme, and experimental results are discussed thoroughly in this paper. [ABSTRACT FROM AUTHOR]

This paper presents an intensive discussion on conducted electromagnetic interference (EMI) emissions from an inverter-driven air conditioner. Common-mode voltages produced by the pulsewidth-modulated (PWM) inverter may cause a high-frequency leakage current. The use of a spectrum analyzer and a line-impedance stabilization network (LISN) makes it possible to refer the leakage current in the time domain to the conducted-EMI emission levels in the frequency domain, which are prescribed by the EMI regulations. Simulation-based estimation of the conducted-EMI emission levels in advance allows engineers to efficiently design a cost-effective EMI filter intended for meeting the regulations. This paper achieves modeling of the inverter-driven air conditioner with focus on common-mode voltages and leakage-current propagation paths. The simulation circuit developed can be used to predict conducted-EMI emission levels and to design the cost-effective EMI filter. Simulated results agree fairly with experimental ones in both cases of the EMI filter being connected and disconnected. [ABSTRACT FROM AUTHOR]

Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. In this first of two consecutive papers, sources of process variations and the state of the art of related simulation tools are reviewed. An approach for hierarchical simulation of process variations including their correlations is presented. The second paper, also published in this issue, presents examples of simulation results obtained with this methodology. [ABSTRACT FROM AUTHOR]

This paper presents and discusses different approaches for the measurements of the shielding effectiveness of thick multilayered panels, based on the use of nested reverberation chambers. In particular, it is considered the case of thick multilayered panels, characterized by one highly reflecting face, like a protected composite laminate or a protected glazing window. The paper proposes a novel test procedure, which allows one to estimate from the measurement of a finite dimension panel, the shielding performance of an infinite material sheet against a reverberating field. The method is validated by comparison with the results of analytical simulations and provides accurate results in a wide frequency range, above the lowest-usable frequency of the outer chamber. [ABSTRACT FROM PUBLISHER]

This paper presents the evaluation of the performance, in terms of uncertainty, of a tool designed to estimate the main parameters of a model of a photovoltaic panel (PVP) under real and/or simulated working conditions. The presented tool permits the characterization of the panel, and it is useful to predict its behavior in whatever working condition; in this way, it is possible to compare the actual and expected performance to prevent any decrease in the output power, so permitting the replacement of the monitored module before it goes out of order or its efficiency falls under a given threshold. The well-known two-diode model is used to estimate the parameters of the electrical equivalent circuit of the PVP and to simulate the I–V and P–V characteristic curves in any given environmental condition of irradiance and/or temperature. The model and the estimation algorithm are implemented with MATLAB functions, whereas data acquisition and result presentation are managed by a LabVIEW graphics user interface. The presented tool has been validated against an experimentally characterized PVP. The environmental parameters of the model such as irradiance and temperature have been set (with their respective uncertainties) during simulations or directly measured during the outdoor tests, whereas the others parameters have been evaluated using a best-fit algorithm on the measured data. The estimation is based on the minimization of a new objective function and on a modified expression of the model resistances, which differ from those mentioned in the available literature. After a review of the state of the art, this paper provides the description of the estimation technique and its validation by means of simulations and experiments. Some results are also provided to illustrate the performance of the proposed test method. [ABSTRACT FROM AUTHOR]

Abstract: Ant colony optimization (ACO) is an optimization computation inspired by the study of the ant colonies’ behavior. This paper presents design and CMOS implementation of the ant colony optimization based algorithm for solving the TSP problem. In order to implement ant colony optimization algorithm in CMOS, we will present a new algorithm. This algorithm is based on the original ant colony optimization but it can be implemented in CMOS. Briefly, pheromone matrix is transformed on the chip area and ants move up-down through the pheromone matrix and they make their decisions. Finally ants select a global path. In previous researches only pheromone values is used, but select the next city in this paper is based on heuristics value and pheromone value. In definition of problem, we use heuristics value as a matrix. Previous researches could not be used for wide type of optimization problem but our chip gives heuristics value initially and we can change initial value of heuristics value according to the optimization problem so this capability increases the flexibility of ACO chip. Simple circuit is used in blocks of our chip to increase the speed of convergence of ACO chip. We use Linear Feedback Shift Register (LSFR) circuit for random number generator in ACO chip. ACO chip has capability of solving the big TSP problem. ACO chip is simulated by HSPICE software and simulation results show the good performance of final chip. [ABSTRACT FROM AUTHOR]

This paper proposes an evaluation method for equivalent circuit model of lithium polymer battery (LiPB), which is widely used in the hybrid electric vehicle (HEV), applying the Bode plot and the numerical method. The accurate circuit parameters are determined by numerical analysis and transfer function that is evaluated from the frequency response of LiPB. Generally, the inductive component of battery has an unexpected influence. However, this method takes account of the effect of increased inductive reactance by the high switching frequency. Moreover, the numerical analysis makes the inductive and capacitive components independent of each other, which results in the more accurate circuit parameters of LiPB. The propriety of the evaluation method proposed in this paper is verified by comparison between the voltage–current profiles of battery equipped in the real HEV and that of simulation result using the circuit parameters with respect to the state of charge (SOC) and frequency. [ABSTRACT FROM PUBLISHER]

This paper focuses on the errors affecting the estimation of power switching losses in power semiconductor devices based on integration of the voltage by current product. It is shown that the measured waveforms are not simply delayed by the probes, but some overshoots and distortions are due to the probes, which may not easily be corrected. These effects are the source of errors, particularly in fast transients. This paper shows analyses of simulation and measurements, including probe models. [ABSTRACT FROM PUBLISHER]

Abstract: This paper reviews the concept of optically injected logic circuits and investigates their implementation in nanometer CMOS technologies. Optically injected circuits are powered via an optical beam, i.e. they do not require a local power supply and distribution network. A complete set of digital cells has been designed and simulated, and key building blocks of the logic family have been fabricated and tested in a standard 180nm CMOS technology. The paper also discusses the design and implementation of optically injected circuits for clock distribution, input/output, analog-to-digital and digital-to-analog conversion. All these circuits are immediately applicable in wireless biomedical implants or contactless smart cards. They can also be used in other systems-on-chip (SoC), in which very low power operation can be replaced by remote-powered operation. [ABSTRACT FROM AUTHOR]

Microfluidics-based biochips enable the precise control of nanoliter volumes of biochemical samples and reagents. They combine electronics with biology, and they integrate various bioassay operations, such as sample preparation, analysis, separation, and detection. Compared to conventional laboratory procedures, which are cumbersome and expensive, miniaturized biochips offer the advantages of higher sensitivity, lower cost due to smaller sample and reagent volumes, system integration, and less likelihood of human error. This paper first describes the droplet-based "digital" microfluidic technology platform and emerging applications. The physical principles underlying droplet actuation are next described. Finally, the paper presents computer-aided design tools for simulation, synthesis and chip optimization. These tools target modeling and simulation, scheduling, module placement, droplet routing, pin-constrained chip design, and testing. [ABSTRACT FROM AUTHOR]

This paper presents a new built-in current sensor (BICS)-based IDDQ testing scheme for complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs). The proposed BICS will employ short detection times and low power dissipation to effectively ensure the reliability of the BICS and reduce the impact of the circuit under test (CUT) during testing. In addition, an IDDQ testing scheme based on the proposed BICS for detecting the abnormal quiescent current is presented. A 16-kB CMOS static random access memory (SRAM) is used as the CUT in this paper to discuss the testing considerations, including fault models and the IDDQ testing strategy. The simulation results show that the proposed BICS has a much improved performance compared with that in previous works. In addition, the physical chip design of the proposed BICS-based IDDQ testing scheme for SRAM testing applications is also implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS technology. The test results show that 100% fault coverage can be achieved with only a 1.23% area overhead penalty. [ABSTRACT FROM AUTHOR]

Abstract-Sensor position uncertainty is known to degrade significantly the source localization accuracy. This paper investigates the use of a single calibration emitter, whose position is known to the sensor array, to reduce the loss in localization accuracy due to sensor position errors that are random. Using a Gaussian noise model, we first derive the Cramér-Rao lower bound (CRLB) for a time difference of arrival (TDOA)-based source location estimate with the use of a calibration source. The differential calibration technique that is commonly used in Global Positioning System through the use of a calibration source to mitigate the inaccuracy in satellite ephemeris data is analyzed. The analysis indicates that differential calibration in most cases cannot reach the CRLB accuracy. The paper then proceeds to propose an algebraic closed-form solution for the source location estimate using both TDOA measurements from the unknown and the calibration source. The proposed algorithm is shown analytically, under high signal-to-noise ratio (SNR) and small sensor position noise, or under moderate level of SNR and sensor position noise together with distant unknown and calibration sources, to reach the CRLB accuracy. Simulations are used to corroborate and support the theoretical development. [ABSTRACT FROM AUTHOR]

As chip multiprocessors with simultaneous multithreaded cores are becoming commonplace, there is a need for simple approaches to exploit thread-level parallelism. In this paper, we consider thread-level speculation as a means to reap thread-level parallelism out of application binaries. We first investigate the tradeoffs between scheduling speculative threads on the same core and on different cores. While threads contend for the same resources using the former approach, the latter approach is plagued by the overhead for inter-core communication. Despite the impact of resource contention, our detailed simulations show that the first approach provides the best performance due to lower inter-thread communication cost. The key contribution of the paper is the proposed design and evaluation of the dual-thread speculation system. This design point has very low complexity and reaps most of the gains of a system. [ABSTRACT FROM AUTHOR]

The modelling of industrial systems is a very hard task because of both the number and diversity of parameters to take into account, and the complex relations between these parameters. In this paper, we are interested on the study of a fully automated Integrated Circuit (IC) semiconductor manufacturing plant (lab). In the semiconductor literature, lab behaviour analysis has very often been performed using discrete-event simulation models, but little work has been devoted to the conceptualisation of the modelling approach. Other works focus on the analysis of single parts of the lab, by simplifying the relations between its components. In such a context, the aim of this paper is to use formal methodologies to model all the components of a wafer lab, that is, its physical and control systems, as well as the fabrication process. This model specification can then be used to build a simulation model for the dynamic factory behaviour analysis. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for fast time-domain simulation of analog systems with nonlinear parameters. Specifically, the paper focuses on analog-to-digital converters (ADC). The method creates compiled-code simulators based on symbolic analysis. Code is optimized using loop invariant elimination and constant folding, well-known compiler optimization methods. Circuits are described as structural macromodels. Nonlinear parameters are expressed using piecewise linear (PWL) models. The paper presents a technique for automatically creating PWL models through model extraction from trained neural networks. As compared to existing behavioral simulation methods for ADC, this technique is more systematic and accurate. In our experiments, compiled-code simulation was significantly faster than numerical simulation. Hence, the methodology is very useful in analog and mixed-signal system synthesis, which is known to require a large number of simulation steps. [Copyright &y& Elsevier]

In this paper, the Newton-Krylov method is explored for robust and efficient time-domain simulation of integrated circuits with large amount of parasitic elements. Different from LU-factorization-based direct methods used in SPICE-like circuit simulators, the Newton-Krylov method uses a preconditioned Krylov-subspace iterative method for solving linearized-circuit equations. A key contribution of this paper is to introduce an effective quasi-Newton preconditioning scheme for Krylov-subspace methods to reduce the number and cost of LU factorization during an entire time-d0main circuit simulation. The proposed quasi-Newton preconditioning scheme consists of four key techniques: 1) a systematic method for adaptively controlling time step sizes; 2) automatically generated piecewise weakly nonlinear (PWNL) definition of nonlinear devices to construct quasi-Newton preconditioners; 3) low-rank update techniques for incrementally updating preconditioners; and 4) incomplete-LU preconditioning for efficiency. Experimental results on a collection of digital, analog, and RF circuits have shown that the quasi-Newton preconditioned Krylov-subspace method is as robust and accurate as the direct method used in SPICE. The proposed Newton-Krylov method is attractive for simulating circuits with massive parasitic RLC elements for postlayout verification. For a nonlinear circuit with power/ground networks with tens-of-thousand elements, the CPU time speedup over SPICE3 is over 20X, and it is expected to increase further with the circuit size. [ABSTRACT FROM AUTHOR]

This paper presents results on fault simulation and response compaction on ISCAS 89 full scan sequential bench- mark circuits using HOPE—a fault simulator developed for synchronous sequential circuits that employs parallel fault simulation with heuristics to reduce simulation time in the context of designing space-efficient support hardware for built-in self-testing of very large-scale integrated circuits. The techniques realized in this paper take advantage of the basic ideas of sequence characterization previously developed and utilized by the authors for response data compaction in the case of ISCAS 85 combinational benchmark circuits, using simulation programs ATALANTA, FSIM, and COMPACTEST, under conditions of both stochastic independence and dependence of single and double line errors in the selection of specific gates for merger of a pair of output bit streams from a circuit under test (CUT). These concepts are then applied to designing efficient space compression networks in the case of full scan sequential benchmark circuits using the fault simulator HOPE. [ABSTRACT FROM AUTHOR]

Millimeter-wave signals are typically generated by frequency multiplication in modern single-chip or multichip module (MCM) systems. Consequently, the multiplication efficiency, spurious rejection, and size of the frequency multiplier ultimately limit the integration level and cost of these systems. This paper points to the size reduction of millimeter-wave frequency doublers by evaluating artificial transmission lines (ATL's) as a means to minimize the size of the low-impedance shunt stubs. As a result, we developed a 40-GHz frequency doubler, which used only 0.6-mm2 area on a monolithic microwave integrated circuit. Despite the area minimization, the doubler exhibited state-of-the-art conversion loss of 1 dB over 10% bandwidth and rejected the fundamental frequency signal by more than 20 dB over 25% bandwidth. Reported herein is the novel simulation of the frequency doubler with active harmonic loads. Included in this paper are theoretical evaluation and simulation of ATL's with models for lumped components and verification of the results by electromagnetic simulation. Due to the high efficiency, low area requirement, and over 20-dB rejection of the fundamental signal, this miniaturized ATL frequency doubler can be used as a building block in the generation of local-oscillator signals in single-chip and MCM millimeter-wave systems [ABSTRACT FROM PUBLISHER]

Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods. [ABSTRACT FROM AUTHOR]

It is known that the ripple-based control of a switching dc–dc converter benefits from a faster transient response than a conventional pulse width modulation (PWM) control switching dc–dc converter. However, ripple-based control switching dc–dc converters may suffer from fast-scale oscillation. In order to achieve fast transient response and ensure the stable operation of a switching dc–dc converter over a wide load range, based on a conventional pulse train (PT) control technique, a peak capacitor current PT (PCC-PT) control technique is proposed in this paper. With a buck converter as an example, the operating modes, steady-state performance, and transient respond performance of a PCC-PT controlled buck converter are presented and assessed. To eliminate fast-scale oscillation, circuit and control parameter design considerations are given. An accurate discrete iteration model of a PCC-PT controlled buck converter is established, based on which the effects of circuit parameters on the stability of the converter operating in a discontinuous current mode (DCM), mixed DCM-continuous conduction mode (CCM), and CCM are studied. Simulation and experimental results are presented to verify the analysis results. [ABSTRACT FROM PUBLISHER]

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC'99 benchmark circuits as well as on industrial test cases. [ABSTRACT FROM AUTHOR]