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The systolic array is a scheme for parallel processing and provides an architecture which is suited to a high-speed operation. Consequently, the systolic array has been applied to the system for which the high-speed processing is required, but not to the system for which the reduction of the circuit scale is required. This paper demonstrates that the principle of the systolic array can be applied as a means of reducing the circuit scale. By the proposed method, the circuit scale can be reduced in the system based on the systolic array, without an appreciable modification of the connection in the array and the control. This paper discusses the Reed-Solomon (RS) coder-decoder based on the systolic array as an example, and shows that the circuit scale can be reduced simply. By this system, the RS coder-decoder can be realized in a simple way by the small circuit scale, corresponding to the processing speed of the system. [ABSTRACT FROM AUTHOR]

This paper considers the Z-channel, which is known as a channel model for photon communication or semiconductor memory. A new decoding algorithm is proposed and discussed. Recently, studies have been made from various viewpoints on the asymmetrical error-correcting code suited to the Z-channel, which is considered interesting. One of the basic problems in the Z-channel is the performance and the decoding method when the cyclic code with various features is applied, but it has been investigated little. This paper presents first a maximum-likelihood decoding algorithm which is highly efficient for the cyclic code on the Z-channel. It is then shown that by providing a certain threshold for the algorithm, a higher-speed decoding is realized. It is shown also that by setting the threshold above a certain value, the computational complexity can be improved without sacrificing the maximum-likelihood property. Finally, it is demonstrated by numerical calculation that the decoding error probability is improved greatly by the decoding algorithm proposed in this paper, together with a drastic improvement in the computational complexity. [ABSTRACT FROM AUTHOR]