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Abstract: A high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an error amplifier, the independence of off-chip capacitor and effective series resistance (ESR) is ensured for different load currents and operating voltages. This circuit is designed and fabricated using a standard CMOS process. The die area is a . The measurement results show that the total error of the output voltage caused by line and load variations is less than ±3% in low quiescent current (Iddq) or low voltage scenarios. Besides, the smallest dropout of the LDO, 0.11V, while the output current is 165mA, the output load is and 20 in parallel. [Copyright &y& Elsevier]

A novel PVT (process, voltage, temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, supply voltage, and temperature (PVT) is detected, respectively. Based on the detected PVT corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output can be adjusted as well. The proposed design is implemented using a typical 90nm CMOS process to justify the slew rate performance. By the on-silicon measurements, the slew rate of output signal is compensated over 26%, the maximum slew rate is 1.65 (V/ns), the maximum data rate is 330MHz given 1.2/0.9V supply voltage with a 20pF load, the core area of the proposed design is 0.056×0.406mm2, and the power consumption is 2.2mW at 330MHz data rate. [ABSTRACT FROM AUTHOR]