On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2\,\times\,VDD Output Buffers.

A novel process and temperature compensation design for 2\,\times\,VDD output buffers is proposed, where the threshold voltages (Vth) of PMOSs and NMOSs varying with process and temperature deviation could be detected, respectively. A prototype 2\,\times\,VDD output buffer using the proposed compensation design is fabricated using a typical 0.18 \mum CMOS process. By adjusting output currents, the slew rate of output signals could be compensated over 117%. The maximum data rate with compensation is 120 MHz in contrast with 95 MHz without compensation, which is measured on silicon with an equivalent probe capacitive load of 10 pF. [ABSTRACT FROM PUBLISHER]