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Phase-change memory (PCM) is an emerging non-volatile memory technology that is based on the reversible and rapid phase transition between the amorphous and crystalline phases of certain phase-change materials. The ability to alter the conductance levels in a controllable way makes PCM devices particularly well-suited for synaptic realizations in neuromorphic computing. A key attribute that enables this application is the progressive crystallization of the phase-change material and subsequent increase in device conductance by the successive application of appropriate electrical pulses. There is significant inter- and intra-device randomness associated with this cumulative conductance evolution, and it is essential to develop a statistical model to capture this. PCM also exhibits a temporal evolution of the conductance values (drift), which could also influence applications in neuromorphic computing. In this paper, we have developed a statistical model that describes both the cumulative conductance evolution and conductance drift. This model is based on extensive characterization work on 10 000 memory devices. Finally, the model is used to simulate the supervised training of both spiking and non-spiking artificial neuronal networks. [ABSTRACT FROM AUTHOR]

There is a significant need to build efficient non-von Neumann computing systems for highly data-centric artificial intelligence related applications. Brain-inspired computing is one such approach that shows significant promise. Memory is expected to play a key role in this form of computing and, in particular, phase-change memory (PCM), arguably the most advanced emerging non-volatile memory technology. Given a lack of comprehensive understanding of the working principles of the brain, brain-inspired computing is likely to be realized in multiple levels of inspiration. In the first level of inspiration, the idea would be to build computing units where memory and processing co-exist in some form. Computational memory is an example where the physical attributes and the state dynamics of memory devices are exploited to perform certain computational tasks in the memory itself with very high areal and energy efficiency. In a second level of brain-inspired computing using PCM devices, one could design a co-processor comprising multiple cross-bar arrays of PCM devices to accelerate the training of deep neural networks. PCM technology could also play a key role in the space of specialized computing substrates for spiking neural networks, and this can be viewed as the third level of brain-inspired computing using these devices. [ABSTRACT FROM AUTHOR]

In spite of decades of research, the details of electrical transport in phase-change materials are still debated. In particular, the so-called threshold switching phenomenon that allows the current density to increase steeply when a sufficiently high voltage is applied is still not well understood, even though there is wide consensus that threshold switching is solely of electronic origin. However, the high thermal efficiency and fast thermal dynamics associated with nanoscale phase-change memory (PCM) devices motivate us to reassess a thermally assisted threshold switching mechanism, at least in these devices. The time/temperature dependence of the threshold switching voltage and current in doped Ge2Sb2Te5 nanoscale PCM cells was measured over 6 decades in time at temperatures ranging from 40 °C to 160 °C. We observe a nearly constant threshold switching power across this wide range of operating conditions. We also measured the transient dynamics associated with threshold switching as a function of the applied voltage. By using a field- and temperature-dependent description of the electrical transport combined with a thermal feedback, quantitative agreement with experimental data of the threshold switching dynamics was obtained using realistic physical parameters. [ABSTRACT FROM AUTHOR]

Electrical transport in chalcogenide-based phase change materials is an active area of research owing to the prominent role played by these materials in the field of information technology. Here, we present transport measurements (IV curves) obtained on line-cells of as-deposited amorphous phase change materials (Ge2Sb2Te5, GeTe, Ag4In3Sb66Te27) over a wide voltage and temperature range (300K to 160 K). The well defined geometry of our devices enables a description of the transport behavior in terms of conductivity vs. electric field. At higher temperatures (300K≥T≥220 K) and low to intermediate fields (F<20 V/µm), the data can be described within the framework of a previously developed model, which is based on multiple trapping transport together with 3D Poole-Frenkel emission from a two-center Coulomb potential. Based on this model, we observe a temperature dependence of the inter-trap distance, which we can relate to a temperature dependence in the occupation of the defect creating the Coulomb potential governing Poole- Frenkel emission. At higher fields and lower temperatures, the dependency of the IV curve on the electric field can be described by ln(I/I0)=(F/Fc)2. By combining this contribution with that of the Poole-Frenkel emission, we can show that the slope at high fields, Fc, is independent of temperature. We argue that models based on direct tunneling or thermally assisted tunneling from a single defect into the valence band cannot explain the observed behavior quantitatively. [ABSTRACT FROM AUTHOR]

Electrical transport in chalcogenide-based phase change materials is an active area of research owing to the prominent role played by these materials in the field of information technology. Here, we present transport measurements (IV curves) obtained on line-cells of as-deposited amorphous phase change materials (Ge2Sb2Te5, GeTe, Ag4In3Sb66Te27) over a wide voltage and temperature range (300K to 160 K). The well defined geometry of our devices enables a description of the transport behavior in terms of conductivity vs. electric field. At higher temperatures (300K≥T≥220 K) and low to intermediate fields (F<20 V/µm), the data can be described within the framework of a previously developed model, which is based on multiple trapping transport together with 3D Poole-Frenkel emission from a two-center Coulomb potential. Based on this model, we observe a temperature dependence of the inter-trap distance, which we can relate to a temperature dependence in the occupation of the defect creating the Coulomb potential governing Poole-Frenkel emission. At higher fields and lower temperatures, the dependency of the IV curve on the electric field can be described by ln(I/I0)=(F/Fc)². By combining this contribution with that of the Poole-Frenkel emission, we can show that the slope at high fields, Fc, is independent of temperature. We argue that models based on direct tunneling or thermally assisted tunneling from a single defect into the valence band cannot explain the observed behavior quantitatively. [ABSTRACT FROM AUTHOR]

In-memory computing is a promising non-von Neumann approach where certain computational tasks are performed within resistive memory units by exploiting their physical attributes. In this paper, we propose a new method for fast and robust compressed sensing (CS) of sparse signals with approximate message passing recovery using in-memory computing. The measurement matrix for CS is encoded in the conductance states of resistive memory devices organized in a crossbar array. In this way, the matrix-vector multiplications associated with both the compression and recovery tasks can be performed by the same crossbar array without intermediate data movements at potential ${O}{(}{1}{)}$ time complexity. For a signal of size ${N}$ , the proposed method achieves a potential ${O}{(}{N}{)}$ -fold recovery complexity reduction compared with a standard software approach. We show the array-level robustness of the scheme through large-scale experimental demonstrations using more than 256k phase-change memory devices. [ABSTRACT FROM AUTHOR]

Chalcogenide phase change materials enable non‐volatile, low‐latency storage‐class memory. They are also being explored for new forms of computing such as neuromorphic and in‐memory computing. A key challenge, however, is the temporal drift in the electrical resistance of the amorphous states that encode data. Drift, caused by the spontaneous structural relaxation of the newly recreated melt‐quenched amorphous phase, has consistently been observed to have a logarithmic dependence in time. Here, it is shown that this observation is valid only in a certain observable timescale. Using threshold‐switching voltage as the measured variable, based on temperature‐dependent and short timescale electrical characterization, the onset of drift is experimentally measured. This additional feature of the structural relaxation dynamics serves as a new benchmark to appraise the different classical models to explain drift. [ABSTRACT FROM AUTHOR]

Spiking neural networks (SNN) are computational models inspired by the brain's ability to naturally encode and process information in the time domain. The added temporal dimension is believed to render them more computationally efficient than the conventional artificial neural networks, though their full computational capabilities are yet to be explored. Recently, in-memory computing architectures based on non-volatile memory crossbar arrays have shown great promise to implement parallel computations in artificial and spiking neural networks. In this work, we evaluate the feasibility to realize high-performance event-driven in-situ supervised learning systems using nanoscale and stochastic analog memory synapses. For the first time, the potential of analog memory synapses to generate precisely timed spikes in SNNs is experimentally demonstrated. The experiment targets applications which directly integrates spike encoded signals generated from bio-mimetic sensors with in-memory computing based learning systems to generate precisely timed control signal spikes for neuromorphic actuators. More than 170,000 phase-change memory (PCM) based synapses from our prototype chip were trained based on an event-driven learning rule, to generate spike patterns with more than 85% of the spikes within a 25 ms tolerance interval in a 1250 ms long spike pattern. We observe that the accuracy is mainly limited by the imprecision related to device programming and temporal drift of conductance values. We show that an array level scaling scheme can significantly improve the retention of the trained SNN states in the presence of conductance drift in the PCM. Combining the computational potential of supervised SNNs with the parallel compute power of in-memory computing, this work paves the way for next-generation of efficient brain-inspired systems. [ABSTRACT FROM AUTHOR]

Always-on TinyML perception tasks in Internet of Things applications require very high energy efficiency. Analog compute-in-memory (CiM) using nonvolatile memory (NVM) promises high energy efficiency and self-contained on-chip model storage. However, analog CiM introduces new practical challenges, including conductance drift, read/write noise, fixed analog-to-digital (ADC) converter gain, etc. These must be addressed to achieve models that can be deployed on analog CiM with acceptable accuracy loss. This article describes AnalogNets: TinyML models for the popular always-on tasks of keyword spotting (KWS) and visual wake word (VWW). The model architectures are specifically designed for analog CiM, and we detail a comprehensive training methodology, to retain accuracy in the face of analog nonidealities, and low-precision data converters at inference time. We also describe AON-CiM, a programmable, minimal-area phase-change memory (PCM) analog CiM accelerator, with a layer-serial approach to remove the cost of complex interconnects associated with a fully pipelined design. We evaluate the AnalogNets on a calibrated simulator, as well as real hardware, and find that accuracy degradation is limited to 0.8%/1.2% after 24 h of PCM drift (8 bits) for KWS/VWW. AnalogNets running on the 14-nm AON-CiM accelerator demonstrate 8.55/26.55/56.67 and 4.34/12.64/25.2 TOPS/W for KWS and VWWs with 8-/6-/4-bit activations, respectively. [ABSTRACT FROM AUTHOR]

Phase Change Memory (PCM) is an emerging technology exploiting the rapid and reversible phase transition of certain chalcogenides to realize nanoscale memory elements. PCM devices are being explored as non-volatile storage-class memory and as computing elements for in-memory and neuromorphic computing. It is well-known that PCM exhibits several characteristics of a memristive device. In this work, based on the essential physical attributes of PCM devices, we exploit the concept of Dynamic Route Map (DRM) to capture the complex physics underlying these devices to describe them as memristive devices defined by a state—dependent Ohm's law. The efficacy of the DRM has been proven by comparing numerical results with experimental data obtained on PCM devices. [ABSTRACT FROM AUTHOR]

Phase Change Memory (PCM) is an emerging technology exploiting the rapid and reversible phase transition of certain chalcogenides to realize nanoscale memory elements. PCM devices are being explored as non-volatile storage-class memory and as computing elements for in-memory and neuromorphic computing. It is well-known that PCM exhibits several characteristics of a memristive device. In this work, based on the essential physical attributes of PCM devices, we exploit the concept of Dynamic Route Map (DRM) to capture the complex physics underlying these devices to describe them as memristive devices defined by a state—dependent Ohm's law. The efficacy of the DRM has been proven by comparing numerical results with experimental data obtained on PCM devices. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) is being actively explored for in-memory computing and neuromorphic systems. The ability of a PCM device to store a continuum of resistance values can be exploited to realize arithmetic operations such as matrix-vector multiplications or to realize the synaptic efficacy in neural networks. However, the resistance variations arising from structural relaxation, 1/f noise, and changes in ambient temperature pose a key challenge. The recently proposed projected PCM concept helps to mitigate these resistance variations by decoupling the physical mechanism of resistance storage from the information-retrieval process. Even though the device concept has been proven successfully, a comprehensive understanding of the device behavior is still lacking. Here, we develop a device model that captures two key attributes, namely, resistance drift and the state dependence of resistance. The former refers to the temporal evolution of resistance, while the latter refers to the dependence of the device resistance on the phase configuration of the phase change material. The study provides significant insights into the role of interfacial resistance in these devices. The model is experimentally validated on projected PCM devices based on antimony and a metal nitride fabricated in a lateral device geometry and is also used to provide guidelines for material selection and device engineering. [ABSTRACT FROM AUTHOR]

The article reports that memristive devices exhibit an electrical resistance that can be adjusted to two or more nonvolatile levels by applying electrical stresses. Topics include considered that the core of the advanced memristive devices is a metal/insulator/metal nanocell made of phase-change, metaloxide, magnetic, or ferroelectric materials, which is placed in series with other circuit elements to enhance their performance in array configurations.