Search

Gradual switching between multiple resistance levels is desirable for analog in-memory computing using resistive random-access memory (RRAM). However, the filamentary switching of HfOx-based conventional RRAM often yields only two stable memory states instead of gradual switching between multiple resistance states. Here, we demonstrate that a thermal barrier of Ge2Sb2Te5 (GST) between HfOx and the bottom electrode (TiN) enables wider and weaker filaments, by promoting heat spreading laterally inside the HfOx. Scanning thermal microscopy suggests that HfOx + GST devices have a wider heating region than control devices with only HfOx, indicating the formation of a wider filament. Such wider filaments can have multiple stable conduction paths, resulting in a memory device with more gradual and linear switching. The thermally enhanced HfOx + GST devices also have higher on/off ratio (>103) than control devices (<102) and a median set voltage lower by approximately 1 V (∼35%), with a corresponding reduction of the switching power. Our HfOx + GST RRAM shows 2× gradual switching range using fast (∼ns) identical pulse trains with amplitude less than 2 V. [ABSTRACT FROM AUTHOR]

The impact of phase change memory (PCM) device non-idealities on the deep neural network (DNN) inference accuracy is systematically investigated. Based on the experimental PCM data, statistical models of device non-idealities were extracted and incorporated into our PyTorch-based simulation framework for evaluations on the CIFAR-10 dataset. Our specific results include: 1) nonlinear ${I}$ – ${V}$ could incur a significant accuracy degradation, but it can be eliminated depending on how the input activations are encoded (e.g., no degradation with pulse-encoding schemes); 2) resistance variation and read noise induce a relatively mild accuracy degradation (< 1% with experimentally fit model), which can be further mitigated through variation-aware training (VAT); 3) maximizing accuracy over a given operating temperature range is attained through a “temperature-specific weight remapping” method developed in this work, accuracy variance of < 3% is demonstrated over a temperature range of ${T} \pm 15 ^{\circ }\text{C}$ ; and 4) resistance drift leads to a significant accuracy degradation over time and is the most challenging non-ideality to address by algorithmic means alone (drift coefficient < 0.015 is needed to achieve < 3% degradation in ten years). A “weight transfusion” (WT) method has been proposed to effectively recover the inference accuracy by incrementally activating additional pre-trained neurons over time. The main overhead is the additional area to store pre-trained weights beforehand, which is likely affordable given the high density of MLC PCM. [ABSTRACT FROM AUTHOR]

In this work, we investigate the temperature-dependent thermal conductivities of few nanometer thick alternating stacks of amorphous dielectrics, specifically SiO2/Al2O3 and SiO2/Si3N4. Experiments using steady-state Joule-heating and electrical thermometry, while using a micro-miniature refrigerator over a wide temperature range (100-500 K), show that amorphous thin-film multilayer SiO2/Si3N4 and SiO2/Al2O3 exhibit through-plane room temperature effective thermal conductivities of about 1.14 and 0.48 W/(m × K), respectively. In the case of SiO2/Al2O3, the reduced conductivity is attributed to lowered film density (7.03 → 5.44 × 1028 m-3 for SiO2 and 10.2 → 8.27 × 1028 m-3 for Al2O3) caused by atomic layer deposition of thin-films as well as a small, finite, and repeating thermal boundary resistance (TBR) of 1.5 m2 K/GW between dielectric layers. Molecular dynamics simulations reveal that vibrational mismatch between amorphous oxide layers is small, and that the TBR between layers is largely due to imperfect interfaces. Finally, the impact of using this multilayer dielectric in a dash-type phase-change memory device is studied using finite-element simulations. [ABSTRACT FROM AUTHOR]

We present a data-calibrated compact model of carbon nanotube (CNT) FETs (CNTFETs) based on the virtual-source (VS) approach, describing the intrinsic current–voltage and charge–voltage characteristics. The features of the model include: 1) carrier VS velocity extracted from experimental devices with gate lengths down to 15 nm; 2) carrier effective mobility and velocity depending on the CNT diameter; 3) short channel effect such as inverse subthreshold slope degradation and drain-induced barrier lowering depending on the device dimensions; and 4) small-signal capacitances including the CNT quantum capacitance effect to account for the decreasing gate capacitance at high gate bias. The CNTFET model captures the dimensional scaling effects and is suitable for technology benchmarking and performance projection at the sub-10-nm technology nodes. [ABSTRACT FROM AUTHOR]

The crystallization times of Ge–Te phase change materials with variable Ge concentrations (29.5–72.4 at. %) were studied. A very strong dependence of the crystallization time on the composition for as-deposited, amorphous films was confirmed, with a minimum for the stoichiometric composition GeTe. The dependence is weaker for melt-quenched, amorphous material and crystallization times are between one to almost four orders of magnitude shorter than for as-deposited materials. This is promising for applications because recrystallization from the melt-quenched phase is the relevant process for optical and solid state memory, and fast crystallization and weak dependence on compositional variations are desirable. [ABSTRACT FROM AUTHOR]