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Presents a study that examined the properties of indium-gallium-arsenic epilayers grown on indium-coated gallium arsenide substrates. Use of photoluminescence measurement; Effects of hydrogenation using a photochemical-vapor-deposition system; Information on the band-edge photoluminescence spectra of the samples used in the study.

Low Vt Ni fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large Vt shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The Vt shifts are preserved down to the shortest gate lengths. For both Al and Yb, the Vt shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low Vt dual implantation approach proposed achieves a low-cost "dual dielectric" implementation without the need of dual deposition of dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-κ dielectric. The Yb diffusion and reaction at the interface can be engineered using a P complaint. [ABSTRACT FROM AUTHOR]

This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy2O3 cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Å Dy2O3 cap resulting in ΔeWF ≈ 400 meV and final eWF ≈ 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Wellbehaved short-channel devices (Lg ∼ 100 nm, SS ∼ 70 mV/dec, and DIBL ∼ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy2O3 cap (5 Å)] devices with NiSi-FUSI gates, corresponding to a similar Tinv (ΔTinv < 1 Å). This capping approach, when combined with Ni-silicide FUSI phase engineering, allows ΔeWF(n-p) values up to ∼800 meV, making it promising for low-VT CMOS. [ABSTRACT FROM AUTHOR]

The mechanism governing threshold voltage (Vt) modulation in NiSi/SiON n-channel metal-oxide-semiconductor field-effect transistors when doping with rare-earth elements (dysprosium or Dy in this work) is studied. In addition to the widely reported interface dipole theory, this letter provides additional evidence that the bulk trapping charges (related to the unintermixed Dy2O3 layer after device fabrication) can play an important role in determining the device Vt for the above-mentioned gate stacks. It is thus suggested that a careful design of the capping layer thickness and the thermal budget for intermixing the capping layer with host dielectrics is necessary to eliminate the impact from bulk trapping charges to the device performance. [ABSTRACT FROM AUTHOR]

This letter reports a novel approach to achieve low threshold voltage (Vt) Ni-FUlly-SIlicide (FUSI) nMOSFETs with SiON dielectrics. By using a Dysprosium-oxide (Dy2O3) cap layer with a thickness of 5 Å on top of the SiON host dielectrics, Vt,lin of 0.18 V for long-channel devices (Lg = 1 μm) using NiSi-FUSI electrode is obtained, satisfying the high-performance device requirements. The Vt modulation due to the Dy2O3 cap layer is also maintained in the short-channel devices (with an Lg,min of 90 nm as demonstrated in this letter). In particular, approximately 150 × reduction in gate leakage current is seen while preserving the dielectric capacitance equivalent thickness after adding the Dy2 O3 cap layer on SiON dielectrics, likely due to a high-k layer (DySiON) formation during device source/drain activation process. We also report that the Dy2 O3 layer does not vitally degrade the device reliability, such as positive-bias temperature instability and time-dependant dielectrics breakdown. [ABSTRACT FROM AUTHOR]

In this letter, we report that by using a thin Dysprosium oxide (Dy2O3) cap layer (~1-nm thick) on top of SION host dielectrics, the threshold voltage (Vt) of poly-Si/TaN gated n-FETs can be modulated to match that of the reference poly-Si/SiON devices, with a significantly scaled equivalent oxide thickness, a much reduced gate leakage, improved time-zero-break-down characteristics, and a minor degradation of the long channel devices mobility. These effects are attributed to the formation of a DySiON layer formation after full device fabrication due to the intermixing between the Dy2O3 cap and the SiON layer, as evidenced by a cross-sectional transmission-electron-microscopy measurement. [ABSTRACT FROM AUTHOR]

In this letter, we report that the application of a thin HfSiON cap layer (2-10 cycles via atomic layer deposition) on SiON host dielectrics in phase-controlled Ni-fully-silicide (FUSI) CMOS technology is effective to modulate the device Vt and reduce the gate leakage while maintaining a similar gate capacitance equivalent thickness and a long channel device mobility (at an Eeff of 0.8 MV/cm). High-Vt ring oscillator with a delay of 17 ps has been demonstrated, with a much-reduced static power (~40 times) as compared to the Ni-FUSI device using the pure SiON dielectrics. It is proposed that the phase-controlled Ni-FUSI technology using the SiON dielectrics capped with thin HfSiON is promising for the 45-nm and beyond low-power CMOS applications. [ABSTRACT FROM AUTHOR]