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Object detection plays a crucial role in various cutting-edge applications, such as autonomous vehicles and advanced robotics systems, primarily relying on conventional frame-based RGB sensors. However, these sensors face challenges such as motion blur and poor performance under extreme lighting conditions. Novel event-based cameras, inspired by biological vision systems, offer a promising solution with superior performance in fast-motion and challenging lighting environments while consuming less power. This work explores the integration of event-based cameras with advanced object detection frameworks, introducing Recurrent YOLOv8 (ReYOLOV8), a refined object detection framework that enhances a leading frame-based YOLO detection system with spatiotemporal modeling capabilities by adding recurrency. ReYOLOv8 incorporates a low-latency, memory-efficient method for encoding event data called Volume of Ternary Event Images (VTEI) and introduces a novel data augmentation technique based on Random Polarity Suppression (RPS) optimized for event-based sensors and tailored to leverage the unique attributes of event data. The framework was evaluated using two comprehensive event-based datasets Prophesee's Generation 1 (GEN1) and Person Detection for Robotics (PEDRo). On the GEN1 dataset, ReYOLOv8 achieved mAP improvements of 5%, 2.8%, and 2.5% across nano, small, and medium scales, respectively, while reducing trainable parameters by 4.43% on average and maintaining real-time processing speeds between 9.2 ms and 15.5 ms. For the PEDRo dataset, ReYOLOv8 demonstrated mAP improvements ranging from 9% to 18%, with models reduced in size by factors of 14.5 × and 3.8 × and an average speed improvement of 1.67 ×. The results demonstrate the significant potential of bio-inspired event-based vision sensors when combined with advanced object detection frameworks. In particular, the ReYOLOv8 system effectively bridges the gap between biological principles of vision and artificial intelligence, enabling robust and efficient visual processing in dynamic and complex environments. The codes are available on GitHub at the following link https://github.com/silvada95/ReYOLOv8. [ABSTRACT FROM AUTHOR]

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach. Memristors hold promise for massively-parallel computing at low power. Aguirre et al. provide a comprehensive protocol of the materials and methods for designing memristive artificial neural networks with the detailed working principles of each building block and the tools for performance evaluation. [ABSTRACT FROM AUTHOR]

DNA pattern matching is essential for many widely used bioinformatics applications. Disease diagnosis is one of these applications since analyzing changes in DNA sequences can increase our understanding of possible genetic diseases. The remarkable growth in the size of DNA datasets has resulted in challenges in discovering DNA patterns efficiently in terms of run time and power consumption. In this paper, we propose an efficient pipelined hardware accelerator that determines the chance of the occurrence of repeatexpansion diseases using DNA pattern matching. The proposed design parallelizes the DNA pattern matching task using associative memory realized with analog content-addressable memory and implements an algorithm that returns the maximum number of consecutive occurrences of a specific pattern within a DNA sequence. We fully implement all the required hardware circuits with PTM 45-nm technology, and we evaluate the proposed architecture on a practical human DNA dataset. The results show that our design is energy-efficient and accelerates the DNA pattern matching task by more than 100× compared to the approaches described in the literature. [ABSTRACT FROM AUTHOR]

Recent works demonstrated that imperceptible perturbations to input data, known as adversarial examples, can mislead neural networks' output. Moreover, the same adversarial sample can be transferable and used to fool different neural models. Such vulnerabilities impede the use of neural networks in mission-critical tasks. To the best of our knowledge, this is the first paper that evaluates the robustness of emerging CNN- and transformer-inspired image classifier models such as SpinalNet and Compact Convolutional Transformer (CCT) against popular white- and black-box adversarial attacks imported from the Adversarial Robustness Toolbox (ART). In addition, the adversarial transferability of the generated samples across given models was studied. The tests were carried out on the CIFAR-10 dataset, and the obtained results show that the level of susceptibility of SpinalNet against the same attacks is similar to that of the traditional VGG model, whereas CCT demonstrates better generalization and robustness. The results of this work can be used as a reference for further studies, such as the development of new attacks and defense mechanisms. [ABSTRACT FROM AUTHOR]

Spinach seeds were irradiated with gamma-rays after that soaked in zinc oxide nanoparticles (ZnO–NPs) at 0.0, 50, 100 and 200 ppm for twenty-four hours at room temperature. Vegetative plant growth, photosynthetic pigments, and proline contents were investigated. Also, anatomical studies and the polymorphism by the SCoT technique were conducted. The present results revealed that the germination percentage was at the maximum values for the treatment of 100 ppm ZnO–NPs (92%), followed by 100 ppm ZnO–NPs + 60 Gy (90%). The application of ZnO–NPs resulted in an enhancement in the plant length. The maximum of chlorophylls and carotenoids content was recorded in the treatment, 100 ppm ZnO–NPs + 60 Gy. Meanwhile, the irradiation dose level (60 Gy) with all ZnO–NPs treatments increased proline content and reached its maximum increase to 1.069 mg/g FW for the treatment 60 Gy combined with 200 ppm ZnO–NPs. Also, the anatomical studies declared that there were variations between the treatments; un-irradiated and irradiated combined with ZnO–NPs plants which reveal that the leave epidermal tissue increased with 200 ppm ZnO–NPs in both the upper and lower epidermis. While irradiated plants with 60 Gy combined with 100 ppm ZnO–NPs gave more thickness of upper epidermis. As well as SCoT molecular marker technique effectively induced molecular alterations between the treatments. Where, SCoT primers targeted many new and missing amplicons that are expected to be associated with the lowly and highly expressed genes with 18.2 and 81.8%, respectively. Also, showed that the soaking in ZnO-NPs was helped for reducing molecular alteration rate, both spontaneous and induced by gamma irradiation. This nominates ZnO–NPs as potential nano-protective agents that can reduce irradiation-induced genetic damage. [ABSTRACT FROM AUTHOR]

Local learning schemes have shown promising performance in spiking neural networks (SNNs) training and are considered a step toward more biologically plausible learning. Despite many efforts to design high-performance neuromorphic systems, a fast and efficient on-chip training algorithm is still missing, which limits the deployment of neuromorphic systems in many real-time applications. This work proposes a scalable, fast, and efficient spiking neuromorphic hardware system with on-chip local learning capability. We introduce an effective hardware-friendly local training algorithm compatible with sparse temporal input coding and binary random classification weights. The algorithm is demonstrated to deliver competitive accuracy in different tasks. The proposed digital system explores spike sparsity in communication, parallelism in vector–matrix operations and process-level dataflow, and locality of training errors, which leads to low cost and fast training speed. The system is optimized under various performance metrics. Taking into consideration energy, speed, resources, and accuracy, the proposed method shows around $10\times $ efficiency over a recent work with a direct feedback alignment (DFA) method and $4.5\times $ efficiency over the spike-timing-dependent plasticity (STDP) method. Moreover, our hardware architecture can easily scale up with the network size at a linear rate. Thus, our method has demonstrated great potential for use in various applications, especially those demanding low latency. [ABSTRACT FROM AUTHOR]

Accelerometers in smart devices have been used to successfully provide valuable information such as early warnings of earthquake activity and health monitoring of buildings. The next important step of using the acceleration measurements from smart devices is to assess building seismic damage, which is a more challenging application. A main challenge is related to the sliding motions of smart devices, which prevents acceleration measurements from directly representing the movement of underlying building floors. To detect and remove sliding motions in acceleration measurements, this paper presents an accurate and robust accelerometer-based stick-slip motion classification framework based on machine learning techniques. Three types of machine learning algorithms are introduced, and their classification performance are compared; support vector machine (SVM), multilayer perception (MLP), and recurrent neural networks (RNN). For the SVM and MLP, three classification conditions are considered: feature selection, non-linear discriminating analysis and classifier comparison. For the RNN, three hyperparameters are considered to find the best performing classification algorithm. Each algorithm is trained and validated with experimental acceleration data from a shaking table test. [ABSTRACT FROM AUTHOR]

In-memory computing is an emerging computing paradigm that overcomes the limitations of exiting Von-Neumann computing architectures such as the memory-wall bottleneck. In such paradigm, the computations are performed directly on the data stored in the memory, which highly reduces the memory-processor communications during computation. Hence, significant speedup and energy savings could be achieved especially with data-intensive applications. Associative processors (APs) were proposed in the seventies and recently were revived thanks to the high-density memories. In this tutorial brief, we overview the functionalities and recent trends of APs in addition to the implementation of each content-addressable memory with different technologies. The AP operations and runtime complexity are also summarized. We also explain and explore the possible applications that can benefit from APs. Finally, the AP limitations, challenges, and future directions are discussed. [ABSTRACT FROM AUTHOR]

Millimeter wave (mmWave) massive multiple-input multiple-output (MIMO) systems typically employ hybrid mixed signal processing to avoid expensive hardware and high training overheads. However, the lack of fully digital beamforming at mmWave bands imposes additional challenges in channel estimation. Prior art on hybrid architectures has mainly focused on greedy optimization algorithms to estimate frequency-flat narrowband mmWave channels, despite the fact that in practice, the large bandwidth associated with mmWave channels results in frequency-selective channels. In this paper, we consider a frequency-selective wideband mmWave system and propose two deep learning (DL) compressive sensing (CS) based algorithms for channel estimation. The proposed algorithms learn critical apriori information from training data to provide highly accurate channel estimates with low training overhead. In the first approach, a DL-CS based algorithm simultaneously estimates the channel supports in the frequency domain, which are then used for channel reconstruction. The second approach exploits the estimated supports to apply a low-complexity multi-resolution fine-tuning method to further enhance the estimation performance. Simulation results demonstrate that the proposed DL-based schemes significantly outperform conventional orthogonal matching pursuit (OMP) techniques in terms of the normalized mean-squared error (NMSE), computational complexity, and spectral efficiency, particularly in the low signal-to-noise ratio regime. When compared to OMP approaches that achieve an NMSE gap of $\mathrm {\{4-10\}\,\,dB}$ with respect to the Cramer Rao Lower Bound (CRLB), the proposed algorithms reduce the CRLB gap to only $\mathrm {\{1-1.5\}\,\,dB}$ , while reducing complexity by two orders of magnitude. [ABSTRACT FROM AUTHOR]

Bio-impedance non-invasive measurement techniques usage is rapidly increasing in the agriculture industry. These measured impedance variations reflect tacit biochemical and biophysical changes of living and non-living tissues. Bio-impedance circuit modeling is an effective solution used in biology and medicine to fit the measured impedance. This paper proposes two new fractional-order bio-impedance plant stem models. These new models are compared with three commonly used bio-impedance fractional-order circuit models in plant modeling (Cole, Double Cole, and Fractional-order Double-shell). The two proposed models represent the characterization of the biological cellular morphology of the plant stem. Experiments are conducted on two samples of three different medical plant species from the family Lamiaceae, and each sample is measured at two inter-electrode spacing distances. Bio-impedance measurements are done using an electrochemical station (SP150) in the range of 100 Hz to 100 kHz. All employed models are compared by fitting the measured data to verify the efficiency of the proposed models in modeling the plant stem tissue. The proposed models give the best results in all inter-electrode spacing distances. Four different metaheuristic optimization algorithms are used in the fitting process to extract all models parameter and find the best optimization algorithm in the bio-impedance problems. [ABSTRACT FROM AUTHOR]

The automatic fitting of spiking neuron models to experimental data is a challenging problem. The integrate and fire model and Hodgkin–Huxley (HH) models represent the two complexity extremes of spiking neural models. Between these two extremes lies two and three differential-equation-based models. In this work, we investigate the problem of parameter estimation of two simple neuron models with a sharp reset in order to fit the spike timing of electro-physiological recordings based on two problem formulations. Five optimization algorithms are investigated; three of them have not been used to tackle this problem before. The new algorithms show improved fitting when compared with the old ones in both problems under investigation. The improvement in fitness function is between 5 and 8%, which is achieved by using the new algorithms while also being more consistent between independent trials. Furthermore, a new problem formulation is investigated that uses a lower number of search space variables when compared to the ones reported in related literature. [ABSTRACT FROM AUTHOR]

Accelerometers in smart devices have been used to successfully detect the occurrence of seismic activity. Taking the next step of using the measured acceleration response to compute floor displacements for the purpose of assessing building seismic damage is a more challenging application. In particular, sliding of smart devices or their underlying support hinders their use for this purpose because that means that the floor drifts cannot be directly measured using the onboard sensors. This paper discusses the dynamic behavior of a free-standing smart device and presents a method for estimating the kinetic coefficient of friction between the smart device and the underlying surface based on wavelet transforms. A methodology is then presented by which a smart device can decide if its motion is representative of the motion of the floor underneath or whether it is tainted by excessive sliding action. The noise associated with a smart device's measurement of acceleration is established and noise reduction methods to overcome them are compared. Computational simulation results and experimental data are used to demonstrate the concepts discussed in this paper. [ABSTRACT FROM AUTHOR]

Assessing the structural integrity of buildings after an earthquake is necessary for citizens to be able to use these facilities safely after the event. The currently available structural health monitoring (SHM) systems use a dense network of sensors installed in buildings to monitor their behavior during earthquakes. Such a network is impractical with respect to cost and deployment time for the vast majority of buildings; therefore, most structures remain uninstrumented. However, a massive network of citizen-owned smart devices, such as tablets and smartphones that contain cameras and vibration sensors, has already been deployed. This paper develops a framework that can crowdsource readings from distributed citizen-owned smart devices and convert these readings into actionable information. Although prior community-based seismic research focused on using smartphones to provide early disaster warnings, the proposed system focuses specifically on using video captured on a smartphone to directly assess the structural health of buildings post-earthquake, thus providing citizens and emergency personnel with immediate relevant information regarding the health state of buildings. This paper presents a novel self-calibration technique for a smartphone camera using its internal accelerometer readings. Shake table experiments show that the proposed technique can achieve sub-millimeter accuracy, demonstrating its suitability for SHM applications. [ABSTRACT FROM AUTHOR]

Various hypotheses of information representation in brain, referred to as neural codes, have been proposed to explain the information transmission between neurons. Neural coding plays an essential role in enabling the brain-inspired spiking neural networks (SNNs) to perform different tasks. To search for the best coding scheme, we performed an extensive comparative study on the impact and performance of four important neural coding schemes, namely, rate coding, time-to-first spike (TTFS) coding, phase coding, and burst coding. The comparative study was carried out using a biological 2-layer SNN trained with an unsupervised spike-timing-dependent plasticity (STDP) algorithm. Various aspects of network performance were considered, including classification accuracy, processing latency, synaptic operations (SOPs), hardware implementation, network compression efficacy, input and synaptic noise resilience, and synaptic fault tolerance. The classification tasks on Modified National Institute of Standards and Technology (MNIST) and Fashion-MNIST datasets were applied in our study. For hardware implementation, area and power consumption were estimated for these coding schemes, and the network compression efficacy was analyzed using pruning and quantization techniques. Different types of input noise and noise variations in the datasets were considered and applied. Furthermore, the robustness of each coding scheme to the non-ideality-induced synaptic noise and fault in analog neuromorphic systems was studied and compared. Our results show that TTFS coding is the best choice in achieving the highest computational performance with very low hardware implementation overhead. TTFS coding requires 4x/7.5x lower processing latency and 3.5x/6.5x fewer SOPs than rate coding during the training/inference process. Phase coding is the most resilient scheme to input noise. Burst coding offers the highest network compression efficacy and the best overall robustness to hardware non-idealities for both training and inference processes. The study presented in this paper reveals the design space created by the choice of each coding scheme, allowing designers to frame each scheme in terms of its strength and weakness given a designs' constraints and considerations in neuromorphic systems. [ABSTRACT FROM AUTHOR]

Traditional convolutional neural network (CNN) architectures suffer from two bottlenecks: computational complexity and memory access cost. In this study, an efficient in-memory convolution accelerator (IMCA) is proposed based on associative in-memory processing to alleviate these two problems directly. In the IMCA, the convolution operations are directly performed inside the memory as in-place operations. The proposed memory computational structure allows for a significant improvement in computational metrics, namely, TOPS/W. Furthermore, due to its unconventional computation style, the IMCA can take advantage of many potential opportunities, such as constant multiplication, bit-level sparsity, and dynamic approximate computing, which, while supported by traditional architectures, require extra overhead to exploit, thus reducing any potential gains. The proposed accelerator architecture exhibits a significant efficiency in terms of area and performance, achieving around 0.65 GOPS and 1.64 TOPS/W at 16-bit fixed-point precision with an area less than 0.25 mm2. [ABSTRACT FROM AUTHOR]

To tackle real-world challenges, deep and complex neural networks are generally used with a massive number of parameters, which require large memory size, extensive computational operations, and high energy consumption in neuromorphic hardware systems. In this work, we propose an unsupervised online adaptive weight pruning method that dynamically removes non-critical weights from a spiking neural network (SNN) to reduce network complexity and improve energy efficiency. The adaptive pruning method explores neural dynamics and firing activity of SNNs and adapts the pruning threshold over time and neurons during training. The proposed adaptation scheme allows the network to effectively identify critical weights associated with each neuron by changing the pruning threshold dynamically over time and neurons. It balances the connection strength of neurons with the previous layer with adaptive thresholds and prevents weak neurons from failure after pruning. We also evaluated improvement in the energy efficiency of SNNs with our method by computing synaptic operations (SOPs). Simulation results and detailed analyses have revealed that applying adaptation in the pruning threshold can significantly improve network performance and reduce the number of SOPs. The pruned SNN with 800 excitatory neurons can achieve a 30% reduction in SOPs during training and a 55% reduction during inference, with only 0.44% accuracy loss on MNIST dataset. Compared with a previously reported online soft pruning method, the proposed adaptive pruning method shows 3.33% higher classification accuracy and 67% more reduction in SOPs. The effectiveness of our method was confirmed on different datasets and for different network sizes. Our evaluation showed that the implementation overhead of the adaptive method regarding speed, area, and energy is negligible in the network. Therefore, this work offers a promising solution for effective network compression and building highly energy-efficient neuromorphic systems in real-time applications. [ABSTRACT FROM AUTHOR]

Aims: Worsening of renal function (WRF) is a common complication in patients with acute decompensated heart failure (ADHF). We aimed to evaluate the role of intrarenal Doppler ultrasound (IRD) in the early prediction of WRF in this patient group. Methods and results: Among 90 patients (age: 57.5 ± 11.1 years; 62% male) hospitalized with ADHF, resistivity index (RI), acceleration time (AT), and pulsatility index (PI) were measured on admission and at 24 and 72 h. WRF was defined as increased serum creatinine ≥0.3 mg/dL from baseline. Adverse clinical outcomes were defined as the composite of death, use of vasopressors, and need for ultrafiltration for refractory oedema. WRF developed in 40% of patients. Mean values of renal AT, RI, and PI on admission were 59.7 ± 15, 0.717 ± 0.08, and 1.5 ± 0.48 ms, respectively. At 24 h, there was significant decrease in AT (to 56.7 ± 10 ms, P = 0.02) and renal RI (to 0.732 ± 0.07; P < 0.001); these changes were maintained up to 72 h. Renal PI showed no significant changes. Independent predictors of WRF were renal AT at 24 h and admission values of renal RI, left ventricular ejection fraction, and plasma cystatin C. Renal AT at 24 h ≥ 57.8 ms had 89% sensitivity and 70% specificity for the prediction of WRF. Independent predictors for adverse clinical outcomes were left ventricular end systolic dimension and WRF. Conclusions: Among ADHF patients receiving diuretic therapy, measurement of renal AT and RI by IRD can help identify patients at increased risk for WRF. [ABSTRACT FROM AUTHOR]

Smartphones are an indispensable tool in modern day-to-day life. Their widespread use has spawned numerous applications targeting diverse domains, such as biomedical, environment sensing, and infrastructure monitoring. In such applications, the accuracy of the sensors at the core of the system is still questionable since these devices are not originally designed for high-accuracy sensing purposes. In this article, we investigate the accuracy limits of one of the commonly used sensors, namely, smartphone accelerometer. We focus on the efficacy of a smartphone as an acceleration measuring device, rather than focusing only on the accuracy of its internal accelerometer chip. This holistic approach includes additional errors that arise from the device operating system, such as sampling time uncertainty. Hence, we propose a novel smart device accelerometer error model that includes the traditional additive noise as well as sampling time uncertainty errors represented by a white Gaussian process. The model is validated experimentally using shake table experiments, and the maximum likelihood estimation (MLE) is used to estimate the sampling time uncertainty standard deviation. Moreover, we derive the Cramer–Rao lower bound (CRLB) of acceleration estimation based on the proposed model. [ABSTRACT FROM AUTHOR]

With the advent of 5G networks means for backhauling network traffic emerged as a major consideration. Densification via small cell deployment has made wired solution cost prohibitive, leading to the adoption of spectrally efficient wireless solutions, namely, Integrated Access and Backhaul (IAB). This paper discusses the different options for IAB and focuses on novel solutions for in-band IAB using Full Duplex (FD) enabled nodes. Dynamically reconfigured beam steering antennas are presented as a means of passively suppressing Self-Interference (SI). Experimental results confirm up to 65 dB of SI cancellation in a harsh environment with obstacle. Finally, robust methods for managing FD practical considerations including timing and frequency offsets are presented, with experimental results confirming performance. [ABSTRACT FROM AUTHOR]

Continuous structural health monitoring of civil infrastructure can be achieved by deploying an Internet of Things network of distributed acceleration sensors in buildings to capture floor movement. Postdisaster damage levels can be computed based on the peak relative floor displacement as specified in government standards. This article uses machine learning approaches to identify the status of buildings postevent based on accelerometer traces. Prior work in the field assumed the use of high-quality accelerometers for displacement estimation. In this article, we focus on using lower quality and cheaper accelerometers, while accounting for noise effects by incorporating noisy data sets in machine learning approaches for classification. A labeled acceleration data set of buildings response to earthquakes was created, where each sample is labeled with its corresponding damage severity. Sensor noise is included in the data set to model nonideal sensors. Classification performance of machine learning algorithms, such as support vector machine, K-nearest neighbor, and convolutional neural network, is presented. Techniques for addressing noise levels are proposed, and the results are compared with regular noise cancellation techniques that adopt high-pass filtering. Note to Practitioners—This article presents a methodology for automatic estimation of buildings status in the aftermath of a natural disaster, such as an earthquake. It focuses on using low-cost inertial sensors, such as accelerometers, to sense buildings’ vibrations and then applying machine learning algorithms to detect damage. Utilizing the convolutional network approach, the proposed methods detect the building damage state with high accuracy. Since this article focuses on using cheap sensors, the cost of deploying a sensor network to monitor buildings is reduced significantly. Deploying this network enables rescue and reconnaissance teams to have a clear view of the most vulnerable structures. [ABSTRACT FROM AUTHOR]

Natural disasters affect structural health of buildings, thus directly impacting public safety. Continuous structural monitoring can be achieved by deploying an Internet of things network of distributed sensors in buildings to capture floor movement. These sensors can be used to compute the displacements of each floor, which can then be employed to assess building damage after a seismic event. The peak relative floor displacement is computed, which is directly related to damage level according to the United States federal agencies standards. With this information, the building inventory can be classified into immediate occupancy, life safety, or collapse prevention categories. In this paper, we propose a zero velocity update technique to minimize displacement estimation error. Theoretical derivation and experimental validation are presented. In addition, we investigate modeling sensor error and interstory drift ratio distribution. Moreover, we discuss the impact of sensor error on the achieved building classification accuracy. [ABSTRACT FROM AUTHOR]

Background: Acute decompensated heart failure (ADHF) is an important cause of hospital admissions, morbidity and mortality. Objectives: To evaluate role of plasma cystatin C in prediction of adverse in-hospital clinical outcome in patients with ADHF. Methods and results: Among 90 patients hospitalized with ADHF, clinical examination and echocardiographic assessment were done. Renal functions including serum urea, creatinine and estimated glomerular filtration rate (eGFR) were followed up daily. Plasma cystatin C was measured on admission and at 24 and 72 hours. The composite in-hospital adverse clinical outcome included the composite of death, need for ultrafiltration for refractory edema and hypotension requiring vasopressors. Mean value of plasma cystatin C on admission was 1822.7±553 mg/l. Independent predictors of the composite adverse in-hospital clinical outcome were left ventricular end-systolic diameter and admission values of plasma cystatin C. Admission plasma cystatin C ≥ 1707.5 mg/l had 80% sensitivity and 72% specificity for the prediction of the composite adverse in-hospital clinical outcome. Conclusions: Among patients hospitalized with ADHF, measurement of plasma cystatin C on admission can identify patients at increased risk for developing in-hospital adverse clinical outcomes. [ABSTRACT FROM AUTHOR]

This paper proposes a hybrid pyramid Discrete-Wavelet-Transform (DWT) Singular-Value-Decomposition (SVD) data hiding scheme for video authentication and ownership protection. The data being hidden will be in the shape of a main color logo image watermark and another secondary Black and White (B&W) logo image. The color watermark will be decomposed to Bit-Slices. A pyramid transform is performed on the Y-frames of a video stream resulting in error images; then, a Discrete Wavelet Transform (DWT) process is implemented using orthonormal filter banks on these error images, and the Bit-Slices watermarks are inserted in one or more of the resulting subbands in a way that is fully controlled by the owner; then, the watermarked video is reconstructed. SVD will be performed on the color watermark Bit-Slices. A secondary B&W watermark will be inserted in the main color watermark using another SVD process. An enhanced detection technique is developed to estimate the Singular Values to reconstruct the original color watermark image. The overall robustness of this scheme is measured when common attacks are applied to the test videos. A main contribution in this research is that the original host video is not required for the extraction process, the good robustness against different attacks specifically compression, transcoding, temporal and geometrical attacks and the duality in the hiding process. The simulation results show that the proposed algorithm achieves well under both the visual and the metric tests. Furthermore, it performed well against intentional and unintentional attacks. The reconstruction was perfect without attacks, while the average Bit-Error-Rates (BER's) achieved under attacks are in the limits of 2% for the color watermark and 5% for the secondary watermark; meanwhile, the mean Peak Signal-to-Noise Ratio (PSNR) is 57 dB. [ABSTRACT FROM AUTHOR]

Computing based on traditional approaches has hit its limits in terms of scalability and power consumption. For this reason, new computing paradigms have started to emerge that aim to perform operations directly in-memory to eliminate data movement costs. Even though traditional in-memory processor architectures together with emerging semiconductor technologies show promise for improving the efficiency of parallel computing, they lack some vital requirements such as flexibility and sequential execution. In this paper, a novel 2-D in-memory computing architecture is proposed. The proposed associative processing architecture is implemented by both CMOS/static random-access memory and ReRAM technologies and employed as an accelerator. As proven by circuit simulations and comparisons on a variety of benchmarks from different domains, the proposed architecture facilitates very efficient in-memory parallel computing together with a high degree of flexibility that results in faster running time in fundamental benchmarks. [ABSTRACT FROM AUTHOR]

Summary: This paper leverages concepts from an existing model to simulate the planar response of a smart device subjected to friction forces induced by an underlying moving plane. An interpolation technique is used to enhance detection of transition points (between sticking and sliding states), which must be accurately identified because of the frequency of their occurrence during seismic motion. The behavior of a smart device on an unconstrained table or desk, which is itself on a moving floor, is introduced and discussed. After validation of the results using experimental data, the revised model is used to study the sliding potential of smart devices on a surface during strong seismic events. Sliding spectra associated with selected ground motions are presented and extended to incorporate the effect of vertical accelerations with the purpose of assessing their influence. It is shown that vertical accelerations have a minimal effect on the sliding behavior of smart devices and that a “probability of exceeding the slip limit” curve can be developed to relate the probability of sticking to a demand parameter that represents the ground motion. [ABSTRACT FROM AUTHOR]

The bottleneck between the processing elements and memory is the biggest issue contributing to the scalability problem in computing. In-memory computation is an alternative approach that combines memory and processor in the same location, and eliminates the potential memory bottlenecks. Associative processors are a promising candidate for in-memory computation, however the existing implementations have been deemed too costly and power hungry. Approximate computing is another promising approach for energyefficient digital system designs where it sacrifices the accuracy for the sake of energy reduction and speedup in error-resilient applications. In this study, approximate in-memory computing is introduced in memristive associative processors. Two approximate computing methodologies are proposed; bit trimming and memristance scaling. Results show that the proposed methods not only reduce energy consumption of in-memory parallel computing but also improve their performance. As compared to other existing approximate computing methodologies on different architectures (e.g., CPU, GPU, and ASIC), approximate memristive in-memory computing exhibits better results in terms of energy reduction (up to 80x) and speedup (up to 20x) on a variety of benchmarks from different domains when quality degradation is limited to 10% and it confirms that memristive associative processors provide a highly-promising platform for approximate computing. [ABSTRACT FROM AUTHOR]

The bottleneck between the processing elements and memory is the biggest issue contributing to the scalability problem in computing. In-memory computation is an alternative approach that combines memory and processor in the same location, and eliminates the potential memory bottlenecks. Associative processors are a promising candidate for in-memory computation, however the existing implementations have been deemed too costly and power hungry. Approximate computing is another promising approach for energyefficient digital system designs where it sacrifices the accuracy for the sake of energy reduction and speedup in error-resilient applications. In this study, approximate in-memory computing is introduced in memristive associative processors. Two approximate computing methodologies are proposed; bit trimming and memristance scaling. Results show that the proposed methods not only reduce energy consumption of in-memory parallel computing but also improve their performance. As compared to other existing approximate computing methodologies on different architectures (e.g., CPU, GPU, and ASIC), approximate memristive in-memory computing exhibits better results in terms of energy reduction (up to 80x) and speedup (up to 20x) on a variety of benchmarks from different domains when quality degradation is limited to 10% and it confirms that memristive associative processors provide a highly-promising platform for approximate computing. [ABSTRACT FROM AUTHOR]

Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8‐SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8‐SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8‐SRAM‐based cache memory. The authors' results show that AS8‐SRAM presents up to 58 times less failures in time compared to six‐transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8‐SRAM achieves up to 22% reduction in energy‐delay product without any considerable loss in performance. [ABSTRACT FROM AUTHOR]

Full-duplex systems are expected to achieve 100% rate improvement over half-duplex systems if the self-interference signal can be significantly mitigated. In this paper, we propose the first full-duplex system utilizing multireconfigurable antenna (MRA) with ∼90% rate improvement compared with half-duplex systems. MRA is a dynamically reconfigurable antenna structure that is capable of changing its properties according to certain input configurations. A comprehensive experimental analysis is conducted to characterize the system performance in typical indoor environments. The experiments are performed using a fabricated MRA that has 4096 configurable radiation patterns. The achieved MRA-based passive self-interference suppression is investigated, with detailed analysis for the MRA training overhead. In addition, a heuristic-based approach is proposed to reduce the MRA training overhead. The results show that at 1% training overhead, a total of 95 dB self-interference cancelation is achieved in typical indoor environments. The 95-dB self-interference cancellation is experimentally shown to be sufficient for 90% full-duplex rate improvement compared with half-duplex systems. [ABSTRACT FROM PUBLISHER]

Full-duplex systems are expected to double the spectral efficiency compared to conventional half-duplex systems if the self-interference signal can be significantly mitigated. Digital cancellation is one of the lowest complexity self-interference cancellation techniques in full-duplex systems. However, its mitigation capability is very limited, mainly due to transmitter and receiver circuit's impairments (e.g., phase noise, nonlinear distortion, and quantization noise). In this paper, we propose a novel digital self-interference cancellation technique for full-duplex systems. The proposed technique is shown to significantly mitigate the self-interference signal as well as the associated transmitter and receiver impairments, more specifically, transceiver nonlinearities and phase noise. In the proposed technique, an auxiliary receiver chain is used to obtain a digital-domain copy of the transmitted Radio Frequency (RF) self-interference signal. The self-interference copy is then used in the digital-domain to cancel out both the self-interference signal and the associated transmitter impairments. Furthermore, to alleviate the receiver phase noise effect, a common oscillator is shared between the auxiliary and ordinary receiver chains. A thorough analytical and numerical analysis for the effect of the transmitter and receiver impairments on the cancellation capability of the proposed technique is presented. Finally, the overall performance is numerically investigated showing that using the proposed technique, the self-interference signal could be mitigated to $\sim$3 dB higher than the receiver noise floor, which results in up to 76% rate improvement compared to conventional half-duplex systems at 20 dBm transmit power values. [ABSTRACT FROM PUBLISHER]

Oscillator phase noise has been shown to be one of the main performance limiting factors in full-duplex systems. In this paper, we consider the problem of self-interference cancellation with phase noise suppression in full-duplex systems. The feasibility of performing phase noise suppression in full-duplex systems in terms of both complexity and achieved gain is analytically and experimentally investigated. First, the effect of phase noise on full-duplex systems and the possibility of performing phase noise suppression are studied. Two different phase noise suppression techniques with a detailed complexity analysis are then proposed. For each suppression technique, both free-running and phase-locked loop-based oscillators are considered. Due to the fact that full-duplex system performance highly depends on hardware impairments that are difficult to fully model, experimental results in a typical indoor environment are presented. The experimental results performed on two different platforms confirm results obtained from numerical simulations. Finally, the tradeoff between the required complexity and the gain achieved using phase noise suppression is discussed. [ABSTRACT FROM PUBLISHER]