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A novel 1440‐V 4H‐SiC accumulation mode MOSFET (ACCUFET) with ultra‐low specific on‐resistance and improved reverse recovery performance is proposed in this article. As for the proposed SiC ACCUFET, the channel region can be completely depleted by the P‐type heavily doped polysilicon gate to build an electron barrier and realize a normally‐off device. And a Schottky barrier diode (SBD) is integrated below the trench gates on both sides, which brings the feasibility of realizing reverse conduction function of the proposed ACCUFET. Also, the p‐shield regions under the Schottky contact metal provide a good electric field shielding effect for the gate oxide. Compared with the conventional SiC trench MOSFET, the numerical simulation results show that the specific on‐resistance (Ron,sp) of the proposed ACCUFET is reduced by more than 64%. The high‐frequency figures‐of‐merit HFOM [Ron,sp × Cgd] and HFOM [Ron,sp × Qgd] of the proposed device are improved by 53.19% and 58.74%, respectively. The reverse recovery time (trr), and reverse recovery charge (Qrr) are reduced by 23.28% and 82.73%, respectively. In addition, the results also indicate that the proposed device has a better latch‐up immunity compared with the conventional SiC trench MOSFET. The excellent device performance and the simple manufacturing process provide a good prospect for the application of the proposed device. [ABSTRACT FROM AUTHOR]

Ultra-wide bandgap semiconductor Ga2O3 based electronic devices are expected to perform beyond wide bandgap counterparts GaN and SiC. However, the reported power figure-of-merit hardly can exceed, which is far below the projected Ga2O3 material limit. Major obstacles are high breakdown voltage requires low doping material and PN junction termination, contradicting with low specific on-resistance and simultaneous achieving of n- and p-type doping, respectively. In this work, we demonstrate that Ga2O3 heterojunction PN diodes can overcome above challenges. By implementing the holes injection in the Ga2O3, bipolar transport can induce conductivity modulation and low resistance in a low doping Ga2O3 material. Therefore, breakdown voltage of 8.32 kV, specific on-resistance of 5.24 mΩ⋅cm2, power figure-of-merit of 13.2 GW/cm2, and turn-on voltage of 1.8 V are achieved. The power figure-of-merit value surpasses the 1-D unipolar limit of GaN and SiC. Those Ga2O3 power diodes demonstrate their great potential for next-generation power electronics applications. The simultaneous achievement of high breakdown voltage and low resistance is a contradictory point because it would require high and low doping simultaneously. Here, Zhou et al. achieve a power figure-of-merit of 13.2 GW/cm2 through hole injection and conductivity modulation effect. [ABSTRACT FROM AUTHOR]

A novel high-performance 1700-V 4H-Silicon carbide (SiC) junction field-effect transistor (JFET) with reverse recovery capability and low switching loss is proposed in this article. As for the proposed 4H-SiC JFET, the gate region of the conventional 4H-SiC JFET is split into two segments, one of which is replaced by the source. A Schottky barrier diode (SBD) is integrated in the sidewall of the channel region, which greatly improves the performances of the 4H-SiC JFET. Compared with the conventional 4H-SiC JFET, the numerical simulation results show that the specific ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON},\text{ sp}}$), gate–drain capacitance (${C}_{\text{GD}}$), and gate–drain charge (${Q}_{\text{gd}}$) of the proposed 4H-SiC JFET are reduced by 25.57%, 99.96%, and 72.91%, respectively. The switching loss is reduced by about 91%, and the average gate drive power consumption is reduced by more than 36% while the frequency range is from 10 to 400 kHz. The results also demonstrate that the proposed device has good reverse recovery performance and reduces switching loss, compared with the current commercial SiC devices. [ABSTRACT FROM AUTHOR]

This article proposes a high-performance trench MOSFET with multiple stepped accumulation layer for conduction enhancement. In the proposed device, a multiple stepped split-gate (SG) is employed and self-biased to form a conductive accumulation layer, which greatly improves the performances of the device. Numerical simulation results show that the specific ON-resistance of the device is 56.41 $\text{m}\Omega \cdot $ mm2 with a breakdown voltage (BV) of ~145 V, which is reduced by 20.3% compared with the conventional trench SG MOSFET. Moreover, the reverse recovery time of the integrated Schottky diode of the proposed device is also reduced by 37.5%, since the multiple stepped accumulation layer can also enhance the conduction capability in the reverse conduction state. In addition, the average gate drive power consumption of the proposed device is reduced by more than 2% when the frequency ranges from 20 to 250 kHz in comparison with that of the conventional one. [ABSTRACT FROM AUTHOR]

This article proposes a new idea to improve the dI/dt and dV/dt controllability of the lateral insulated gate bipolar transistor (LIGBT). By employing an inversion layer thyristor T to enhance the conductivity modulation and applying the startup nMOS M4 with small Miller capacitance, the proposed LIGBT not only realizes low saturation current, but also eliminates the Miller plateau. The simulation results demonstrate that the saturation current with a value of 682 A/cm2 is reduced by 55.5%, and the short-circuit time is improved by 375% in comparison with that of the self-adjust conductivity modulation LIGBT (SCM-LIGBT) silicon-on-insulator LIGBT (SOI-LIGBT). Especially, the dV/dt and dI/dt controllability are improved by 21% and 49%, respectively, since the Miller plateau is basically eliminated. [ABSTRACT FROM AUTHOR]

A novel double-reduced surface field technique (RESURF) insulated gate bipolar transistor based on lateral insulated gate bipolar transistor based on silicon-on-insulator (SOI-LIGBT) with deep-trench-cathode and self-biased pMOS is proposed and investigated by numerical simulation. The proposed SOI-LIGBT remarkably features a deep trench, a self-biased pMOS, a carrier stored layer (n-CS), and p-shield region at the cathode side. Thanks to the n-CS, the proposed device achieves a low ON-state voltage (VON). And the doping concentration of the n-CS (NCS) has almost no impact on the breakdown voltage (BV). Benefited from the self-biased pMOS, the proposed device shows low saturation current and extended short-circuit current withstand-time. In addition, the proposed structure achieves a low turn-off loss (EOFF). Simulation results reveal that, compared with the conventional double-RESURF SOI-LIGBT, the proposed structure achieves 15% VON reduction and 50% saturation current reduction. In addition, the proposed device can sustain the short circuit current for 90% longer time than the conventional double-RESURF SOI-LIGBT. [ABSTRACT FROM AUTHOR]

In this article, a novel diode-clamped carrier stored trench IGBT (DC-CS-TIGBT) is proposed and investigated by the TCAD tool. Two series-connected diodes implemented on the surface of the IGBT is proposed to clamp the voltage potential of the carrier stored layer (CSL). Hence, the CSL can be heavily doped. A significant improvement in the tradeoff between ON-state voltage (VON) and turn-off loss (EOFF) can be achieved due to enhanced emitter injection. Moreover, due to the shielding effect on the voltage potential of the CSL, the saturation current is reduced by over 41% compared with that of the buried P-shield CS-TIGBT(PS-CS-TIGBT). Consequently, the withstand time of short-circuit is improved from 6.7 to 15~μs compared with that of the PS-CS-TIGBT. [ABSTRACT FROM AUTHOR]

A novel composite device structure with enhanced conductivity modulation silicon on insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) which consists of a normal LIGBT (NLT) region, an nMOS region (NM) and a pMOS region (PM) is proposed in this article. By employing a parasitic n-p-n bipolar transistor, the thyristor in the NLT performs a high electron current in ON-state. As a result, the conductivity modulation in the NLT region is dramatically enhanced, which leads to the improvement of the current capability and the forward ON-state voltage drop. In addition, due to the parasitic diode in the substrate of NM, the potential of p-base of the NLT can be clamped at the ON-state voltage drop of the diode, which guarantees the current saturated capability of the LIGBT. [ABSTRACT FROM AUTHOR]

A novel reverse-conducting (RC) lateral insulated gate bipolar transistor based on the silicon-on-insulator (SOI-LIGBT) with integrated parallel/antiparallel polysilicon diodes ($\text{D}_{F}$ and $\text{D}_{R}$) on the top of the anode active region is proposed and investigated by simulation. During the turn-off transient, the major part of the excess electron current flows through the parallel diode $\text{D}_{F}$ which achieves a low turn-off loss ($E_{ \mathrm{\scriptscriptstyle OFF}}$). While during the forward-conducting state, the voltage across the p+-anode/n-buffer junction can rapidly increase to the junction’s built-in potential (${V}_{\text {bi}}$) at low anode current, which results in snapback immunity. Moreover, the antiparallel diode $\text{D}_{R}$ enables the proposed device to realize RC capability. Simulation results reveal that the proposed RC-LIGBT can realize superior $E_{ \mathrm{\scriptscriptstyle OFF}}$ - $V_{ \mathrm{\scriptscriptstyle ON}}$ tradeoff relationship than both the conventional LIGBT and the separated shorted-anode LIGBT (SSA-LIGBT). When $E_{ \mathrm{\scriptscriptstyle OFF}}$ is 0.44 mJ/cm2, $V_{ \mathrm{\scriptscriptstyle ON}}$ of the proposed RC-LIGBT is 1.95 V, which is 0.47 V lower than that of the SSA-LIGBT. Under ${V}_{ \mathrm{\scriptscriptstyle ON}}$ of 1.95 V, $E_{ \mathrm{\scriptscriptstyle OFF}}$ of the proposed RC-LIGBT is 0.44 mJ/cm2, which is reduced by 44.3% than that of the conventional LIGBT. Furthermore, the reverse recovery charge (${Q}_{\text {rr}}$) of the proposed device is reduced by 25.8% compared with that of the conventional one. In addition, diodes $\text{D}_{F}$ and $\text{D}_{R}$ and the thin oxide layer below can be fabricated during the implementation of the polysilicon gate. Therefore, there is no extra difficulty in the fabrication process of the proposed RC-LIGBT. [ABSTRACT FROM AUTHOR]

In this paper, a super-junction p-type lateral diffused metal–oxide–semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed. The proposed SJ-pLDMOS has an n-channel in the drain region and is controlled by an auto-generated voltage signal (${V}_{\mathrm {\textsf {Gn}}}$). The voltage signal ${V}_{\mathrm {\textsf {Gn}}}$ is generated during the ON- and OFF-state of the hole current which flows across an integrated resistor (${R}\text{p}$) implemented in the p-base region. Thus, the proposed SJ-pLDMOS utilizes both hole and electron currents to significantly enhance the current capability. Simulation results show that the current capability of the proposed SJ-pLDMOS without any conductivity modulation effect is comparable with that of a super-junction nLDMOS (SJ-nLDMOS). The total power loss of the proposed super-junction pLDMOS (SJ-pLDMOS) is reduced by about 26.7% and 18% compared with that of the SJ-nLDMOS and Triple Resurf nLDMOS (TR nLDMOS) at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ , respectively. [ABSTRACT FROM AUTHOR]

A novel ultralow turn-off loss silicon-on-insulator-lateral insulated-gate bipolar transistor (LIGBT) is proposed and investigated by numerical simulations. The proposed LIGBT features a high-voltage p-i-n diode integrated on the field oxide that is located upon the surface of the drift region. The p-i-n diode serves as a high-voltage level shifter, and the gate signal of the LIGBT can be transmitted to the anode side of the LIGBT to control a low-voltage circuit which is used to short the p-anode/n-buffer junction when the device is turning off. Thus, the injection of the holes from the p-anode region into the n-drift region is prevented, and the turn-off speed of the proposed LIGBT is significantly improved in comparison with the conventional one. The numerical simulation results reveal that the turn-off loss of the proposed 352-V LIGBT is 43.1% of the conventional LIGBT at VON = 1.38 V. [ABSTRACT FROM AUTHOR]

A new concept high-voltage pseudo-p-channel lateral double-diffused MOS (p-LDMOS) with multiple current paths for conduction is proposed and investigated in this paper. The proposed power device consists of two hole current paths (p-channel MOS device) and one electron current path (n-channel MOS device). The gate of the n-channel device is automatically controlled by an induced signal inside the chip, thus the proposed device can be considered as a p-LDMOS with more than 66.2% reduction of specific on-resistance in comparison with the conventional p-LDMOS device. Furthermore, the proposed device has a much better safe operation area, since the compensation of the electric flux density brought by electron and hole currents. [ABSTRACT FROM AUTHOR]

In this letter, a p-channel lateral double-diffused MOSFET (p-LDMOS) with double electron paths used to enhance the current capability is proposed. The proposed p-LDMOS has two n-channels that are controlled by an auto-generated voltage signal (${V}_{\text {Gn}}$). The voltage signal ${V}_{\text {Gn}}$ is generated during the ON and OFF states of the hole current that flows across an integrated resistor ($R_{\text {p}}$) implemented in the P-base region. Thus, the current capability of the p-LDMOS can be significantly enhanced by the introduced electron current. The simulation results show that the current capability of the proposed p-LDMOS can be comparable to that of the n-type triple RESURF technique without any conductivity modulation effect. The power loss of the proposed p-LDMOS is reduced by approximately 78.6% and 15.6% compared with the triple RESURF p-LDMOS and n-LDMOS, respectively, at a rated load current density of $25~\mu \text{A}/\mu \text{m}$. [ABSTRACT FROM AUTHOR]

Two dual channel three-terminal transmission-gate-like n-p-lateral double-diffused metal oxide semiconductor (n-p-LDMOS) power devices with majorities of both types for conduction are proposed. Based on the method of generating a control signal for one of the gates inside the devices, each proposed n-p-LDMOS device only needs one gate control signal. One of the power devices can be used as an n-LDMOS device and the other can be used as a p-LDMOS device. The safe operating area is widened than the conventional n-LDMOS because of the compensation of electric flux density introduced by electron and hole currents. In addition, the specific ON-resistances of the new devices are reduced by \sim20\% and over 23% compared with that of the conventional n-LDMOS, respectively. The proposed power devices and their control methods are analyzed and verified by numerical simulations. [ABSTRACT FROM AUTHOR]

A novel integrated solution for two high voltage power n-channel mosfet transistors (NMOSTs) MH and ML and two level-shifting high-voltage NMOSTs M1 and M2 are proposed to save chip area and reduce process complexity. The optimized variation lateral doping technique is used for designing the four NMOSTs. The four NMOSTs are isolated by PN junction isolation technique to integrate together. The isolation areas between ML and M1 and M1 and M2 are needed to sustain high voltage in X-direction. Hence, the effective surface charge density distribution in the isolation areas is designed almost the same as the NMOST. The layout area of the two level-shifting high-voltage NMOSTs of the proposed solution is only 6.61% of that conventional one. The simulation results from TCAD MEDICI and DAVINCI show that the expectant functions are well achieved. [ABSTRACT FROM PUBLISHER]