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An analysis of charge pump design for improved radiation tolerance of phase locked loops is presented. Two radiation-hardened-by-design approaches are considered to mitigate the total ionizing dose damage of the circuit, and a thick-film SOI SiGe process technology has been used to reduce charge collection of single event strikes. The results show that a modified design approach to implement the charge pump using SiGe HBTs can provide advantages in radiation tolerance to improve tri-state leakage performance, particularly for missions expecting large accumulated doses. [ABSTRACT FROM PUBLISHER]

We present results on the effects of ELDRS at dose rates of 10, 5, 1, and 0.5 mrad(Si)/s for a variety of commercial, radiation hardened, and ELDRS-free devices. We observed low dose rate enhancement below 10 mrad(Si)/s in several different part types. The magnitudes of the low dose rate enhancement varied substantially. The most notable case showed dose rate sensitivity in the functional failures for a commercial voltage regulator, with initial failures occurring after 10 krad(Si) for the parts irradiated at 0.5 mrad(Si)/s. Radiation hardened and ELDRS-free devices also showed ELDRS at the ultra-low dose rates. An ELDRS-free high power regulator showed a low dose rate enhancement factor of \times33 after 10 krad(Si) for parts irradiated at 0.5 mrad(Si)/s. The enhanced degradation at the ultra-low dose rates present challenges for hardness assurance. [ABSTRACT FROM PUBLISHER]

Many bipolar linear integrated circuits have been shown to exhibit enhanced low dose rate sensitivity (ELDRS), where a product may have worse total ionizing dose (TID) performance when exposed to ionizing radiation at a low dose rate (LDR) than when exposed at a high dose rate (HDR). Recent studies on test cells have suggested that submicron CMOS processes may also exhibit ELDRS. Some CMOS products, although not considered to be BiCMOS, do contain active bipolar elements using the parasitic bipolar structures present in all bulk CMOS processes. Three mixed-signal CMOS products, one digital-to-analog converter (DAC) and two analog-to-digital converters (ADC), using different submicron CMOS processes and using active parasitic bipolar structures were put through LDR TID testing to determine if actual products exhibit ELDRS. MIL-STD-883 TM1019 contains a test method to qualify products that fail HDR TID testing for LDR environments by using HDR testing along with a room temperature anneal. This test method was previously demonstrated on supermicron process nodes. It has been suggested that this test method is not valid for submicron processes. The test method was validated on a submicron CMOS product using the LDR test data from one of the products in this study. [ABSTRACT FROM AUTHOR]

We report heavy-ion microbeam and total dose data for a new complementary (npn + pnp) SiGe on thick-film SOI technology. Measured transient waveforms from heavy-ion strikes indicate a significantly shortened single-event-induced transient current, while maintaining the total dose robustness associated with SiGe devices. Heavy-ion broad-beam data confirm a reduced single event upset (SEU) cross-section in a high-speed shift register circuit. [ABSTRACT FROM AUTHOR]

An accelerated total ionizing dose (TID) hardness assurance test for enhanced low dose rate sensitive (ELDRS) bipolar linear circuits, using high dose rate tests on parts that have been exposed to molecular hydrogen, has been proposed and demonstrated on several ELDRS part types. In this study several radiation-hardened “ELDRS-free” part types have been tested using this same approach to see if the test is overly conservative. [ABSTRACT FROM AUTHOR]

A novel approach to dynamic SEE ADC testing is presented. The benefits of this test scheme versus prior implemented techniques include the ability to observe ADC SEE errors that are in the form of phase shifts, single bit upsets, bursts of disrupted signal composition, and device clock loss. [ABSTRACT FROM AUTHOR]

The Single Event Effect (SEE) characterization of a Digital to Analog Converter showed an unexpected Single Event Transient (SET) dependence on operating conditions. The worst case condition resulting in the highest probability of an SET was at the highest supply voltage. The SET signatures were dependent on the input code, with some signatures not present when the input code was at mid scale. The SET characterization results are presented, along with a simulation study that explains the SET response dependence on the operating conditions. These results emphasize the importance of running an SEE characterization on a mixed signal product and monitoring all aspects of the SET signatures, including probability, amplitude, pulse width and oscillatory behavior, to determine the worst case operating conditions. [ABSTRACT FROM AUTHOR]

Typical test methods for characterizing the single event upset performance of an analog to digital converter (ADC) have involved holding the input at static values. As a result, output error signatures are seen for only a few input voltage and output codes. A test method using an input beat frequency and output code error detection allows an ADC to be characterized with a dynamic input at a high frequency. With this method, the impact of an ion strike can be seen over the full code range of the output. The error signatures from this testing can provide clues to which area of the ADC is sensitive to an ion strike. [ABSTRACT FROM AUTHOR]