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Utilizing Ag/HfO2 with nickel (Ni) as a barrier layer, a novel threshold switching (TS) device is devised to overcome challenges such as low reliability, high threshold voltage, and high leakage current. Compared against an Ag/Ti/HfO2-based TS device, the Ag/Ni/HfO2-based TS device exhibits improved electrical characteristics: yield enhancement from 31.7 % to 40.0 %, enhanced endurance from ∼10 cycles to ∼300 cycles, and suppression in off-state current (IOFF) from 1.2 × 10−7 A to 5.2 × 10−10 A under a high compliance current (e.g., 10−4 A). The results obtained through transmission electron microscopy (TEM), energy-dispersive X-ray spectroscopy (EDS), and atomic force microscopy (AFM) support the evidence of those accomplishments. Reducing the effective area of the TS device improves control over erratically generated filaments and the electric field within the switching layer, resulting in enhanced performance such as a reduced threshold voltage (VTH ∼0.35 V), minimized VTH variability (∼0.01 V), decreased a threshold current (ITH, i.e., the leakage current in the off-state before activation, ∼5.2 × 10−10 A), and maximum conductance (∼5.0 × 10−5 S) of low-resistance state. These findings suggest that the optimized Ag/Ni/HfO2-based TS device can serve as a practical solution for low-power applications.

Superior scalability and better gate-to-channel capacitive coupling can be achieved with adopting gate-all-around (GAA) device architecture. However, compared against FinFET device structure, the GAA device is not very cost-effective. In addition, its yield for mass production is not as high as expected. In order to explore the device design option for extending the current FinFET device out, we have come up with a new idea, i.e., novel device structure to increase the effective channel width without affecting the contacted poly pitch (CPP). A novel u-FinFET structure is a type of FinFET that has a u-shaped channel. By using 3-D TCAD simulation, it turned out that the u-FinFET (vs. conventional bulk/SOI FinFETs) shows a 27.3% higher drain current at $V_{\mathrm {GS}}$ = 0.7 V because of its 28.7% wider effective channel width. Especially, the u-FinFET can be adopted for high performance applications because it can implement a wider channel width for a given layout area. Moreover, taking advantages of using the current processes and materials for bulk/SOI FinFET, the u-FinFET can be fabricated (which must be very cost-effective). Hence, with taking advantages of using the u-FinFET structure, the current FinFET platform would last more.

Abstract In this work, the impact of fluorine (CF4) and oxygen (O2) plasma passivation on HfZrOx (HZO) based ferroelectric capacitor was investigated. By the fluorine passivation, the surface trap density and oxygen vacancies in the HZO-based Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors were suppressed, resulting in the increased pristine remnant polarization (2Pr). The pristine value (2Pr) of baseline samples annealed at 500 °C and 600 °C were 11.4 µC/cm2 and 24.4 µC/cm2, respectively. However, with the F–passivation, the 2Pr values were increased to 30.8 µC/cm2 and 48.2 µC/cm2 for 500 °C and 600 °C, respectively. The amount of surface defects and oxygen vacancies are quantitatively confirmed by the conductance method and XPS analysis. However, due to the incorporation of fluorine atoms into the ferroelectric–insulator films, undesirable degradation on endurance characteristics were observed.

Abstract Continued research on the epidermal electronic sensor aims to develop sophisticated platforms that reproduce key multimodal responses in human skin, with the ability to sense various external stimuli, such as pressure, shear, torsion, and touch. The development of such applications utilizes algorithmic interpretations to analyze the complex stimulus shape, magnitude, and various moduli of the epidermis, requiring multiple complex equations for the attached sensor. In this experiment, we integrate silicon piezoresistors with a customized deep learning data process to facilitate in the precise evaluation and assessment of various stimuli without the need for such complexities. With the ability to surpass conventional vanilla deep regression models, the customized regression and classification model is capable of predicting the magnitude of the external force, epidermal hardness and object shape with an average mean absolute percentage error and accuracy of

For higher density of transistors in Integrated Circuit (IC), various scaling technologies have been introduced. In the light of the physical limit in advancing single-gate transistor architecture, the structural transition from planar device architecture toward 3D device architecture (of which the representative one is Fin-shaped Field-Effect Transistor, or FinFET) manifests itself. However, during fabrication, the unexpected process-induced random variations of the transistor’s electrical characteristics have become more extreme with aggressively scaling down the physical dimension of transistor as well as with evolving from 2D to 3D device structure. Consequently, accurate and rapid estimation of the random variations conditioned on the variation sources (e.g., LER, RDF, and WFV) is required. Recently, machine learning-based approaches were utilized to estimate the LER-induced variations, but they were highly dependent on modeling and evaluation assumptions (e.g., Gaussian or independence). To that end, firstly, we introduce a GAN-based framework for the estimation of process-induced random variations. Since GAN is free from distributional assumptions, this enables precise prediction and, more importantly, enables unified estimation, i.e., adaptable to various variation sources. Secondly, to achieve better generalization on unseen conditions, we additionally suggest a two-step learning strategy utilizing the latest Conditional GAN models. Thirdly, we introduce sample-based evaluation procedure which measures the difference between two sample sets from a probabilistic perspective. Finally, the evaluation results on LER and RDF/WFV datasets show that our GAN-based framework is computationally efficient and is able to generate synthetic samples similar to the TCAD simulated samples that contain random variations, both qualitatively and quantitatively. From such results, our GAN-based framework is expected to be successfully applied to real data, and consequently be able to reliably estimate the random variations of fabricated transistors with multiple orders of magnitude speed-up compared to the conventional TCAD simulation-based estimation.

To design a device that is robust to process-induced random variation, this study proposes a machine-learning-based predictive model that can simulate the electrical characteristics of FinFETs with process-induced line-edge roughness. This model, i.e., a Bayesian neural network (BNN) model with horseshoe priors (Horseshoe-BNN), can significantly reduce the simulation time (as compared to the conventional technology computer-aided design (TCAD) simulation method) in a sufficiently accurate manner. Moreover, this model can perform autonomous model selection over the most compact layer size, which is necessary when the amount of data must be limited. The mean absolute percentage error for the mean and standard deviation of the drain-to-source current $\left ({\mathrm {I}_{\mathrm {DS}} }\right)$ were ~0.5% and ~6%, respectively. By estimating the distribution of the current-voltage characteristics, the distributions of the other device metrics, such as off-state leakage current and threshold voltage, can be estimated as well.

The present study examined the longitudinal measurement invariance of the Korean version of the Center for Epidemiological Studies-Depression (CES-D) scale. For this purpose, two datasets from the Korean Welfare Panel Study were analyzed. Study 1 examined the data from the first four waves to determine the scale’s short-term longitudinal invariance. Study 2 extracted data every 3 years up to the 10th year, beginning with the first wave (waves 1, 4, 7, and 10) to examine the scale’s long-term longitudinal invariance. We analyzed 10,098 cases in Study 1 and 7,077 cases in Study 2. The results of Study 1 revealed that the scale had strict or residual measurement invariance, whereas the results of Study 2 indicated that the scale had strong or scalar measurement invariance. Overall, the Korean version of the CES-D-11 scale was shown to be a valid measure of depression that can be used to evaluate symptom changes over time.

Abstract To address the demands of emerging data‐centric computing applications, ferroelectric field‐effect transistors (Fe‐FETs) are considered the forefront of semiconductor electronics owing to their energy and area efficiency and merged logic–memory functionalities. Herein, the fabrication and application of an Fe‐FET, which is integrated with a van der Waals ferroelectrics heterostructure (CuInP2S6/α‐In2Se3), is reported. Leveraging enhanced polarization originating from the dipole coupling of CIPS and α‐In2Se3, the fabricated Fe‐FET exhibits a large memory window of 14.5 V at VGS = ±10 V, reaching a memory window to sweep range of ≈72%. Piezoelectric force microscopy measurements confirm the enhanced polarization‐induced wider hysteresis loop of the double‐stacked ferroelectrics compared to single ferroelectric layers. The Landau–Khalatnikov theory is extended to analyze the ferroelectric characteristics of a ferroelectric heterostructure, providing detailed explanations of the hysteresis behaviors and enhanced memory window formation. The fabricated Fe‐FET shows nonvolatile memory characteristics, with a high on/off current ratio of over 106, long retention time (>104 s), and stable cyclic endurance (>104 cycles). Furthermore, the applicability of the ferroelectrics heterostructure is investigated for artificial synapses and for hardware neural networks through training and inference simulation. These results provide a promising pathway for exploring low‐dimensional ferroelectronics.

Line-edge-roughness (LER) is one of undesirable process-induced random variation sources. LER is mostly occurred in the process of photo-lithography and etching, and it provokes random variation in performance of transistors such as metal oxide semiconductor field effect transistor (MOSFET), fin-shaped field effect transistor (FinFET), and gate-all-around field effect transistor (GAAFET). LER was analyzed/characterized with technology computer-aided design (TCAD), but it is fundamentally very time consuming. To tackle this issue, machine learning (ML)-based method is proposed in this work. LER parameters (i.e., amplitude, and correlation length X, Y) are provided as inputs. Then, artificial neural network (ANN) predicts 7-parameters [i.e., off-state leakage current (Ioff), saturation drain current (Idsat), linear drain current (Idlin), low drain current (Idlo), high drain current (Idhi), saturation threshold voltage (Vtsat), and linear threshold voltage (Vtlin)] which are usually used to evaluate the performance of FinFET. First, how datasets for training process of ANN were generated is explained. Next, the evaluation method for probabilistic problem is introduced. Finally, the architecture of ANN, training process and our new proposition is presented. It turned out that the prediction results (i.e., non-Gaussian distribution of device performance metrics) obtained from the ANN were very similar to that from TCAD in the respect of both qualitative and quantitative comparison.

A two-dimension (2D) atomic-threshold-switching field-effect transistor (ATS-FET) was implemented, by connecting an AgTi/HfO2-based threshold-switching (TS) device in series to the drain electrode of the 2D baseline-FET with molybdenum disulfide (MoS2) channel material. We optimized/developed the Ag/HfO2-based TS device because its characteristic is associated to the way how to achieve high performance of the 2D ATS-FET. By reducing the effective device area of the Ag/HfO2-based TS device down to $4~\mu \text{m}^{2}$ , low threshold voltage ( $\text{V}_{\mathrm {T}} \sim 0.42$ V), low threshold current (IT, drain current at the threshold voltage, $\sim 3.79 \times 10^{-11}$ A), and low VT variation (~0.09 V) were achieved. This is because the randomly formed filaments and electric field are better controlled with the scaled effective area. Next, the titanium (Ti)-injection barrier layer was inserted between the top electrode and the switching layer, while maintaining the optimized area in the TS device. The inserted Ti-injection barrier layer prevents the migration of Ag ions into the switching layer, enabling the stable TS operation even under the compliance current of $100~\mu \text{A}$ . Additionally, it locally restricts the region where the filaments are created inside the switching layer, resulting in a 17% lower VT variation and stable IT to approximately $\sim 1.5 \times 10^{-11}$ A in 100 cycles. Due to the low off-state leakage current and low variation characteristic of the optimized AgTi/HfO2-based TS device, the 2D ATS-FET (vs. 2D baseline-FET) shows the reduction of off-state leakage current (by $\sim 10^{2}$ in sub-threshold region) and the stable switching characteristic. The proposed 2D ATS-FET shows stably steep switching characteristics, e.g., sub-threshold swing under forward bias (~19 mV/decade) and reverse bias (~26 mV/decade), because of its abruptly switching characteristics of the TS device.

Abstract In this work, the measured electrical characteristics of a fully depleted silicon-on-insulator (FDSOI) device and fin-shaped field-effect transistor (FinFET), whose gate electrode is connected in series to the bottom electrode of a ferroelectric capacitor (FE-FDSOI/FE-FinFET), are experimentally studied. The hysteretic property in input transfer characteristic of those devices is desirable for memory device applications, so that the understanding and modulating the hysteresis window is a key knob in designing the devices. It is experimentally observed that the hysteresis window of FE-FDSOI/FE-FinFET is decreased with (i) increasing the area of the ferroelectric capacitor and/or (ii) decreasing the gate area of baseline FET. The way how to control the hysteresis window of FE-FDSOI/FE-FinFET is proposed and discussed in detail.

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS)

Previous studies have suggested that the operating voltage and energy-delay properties of a nanoelectromechanical (NEM) system can be improved using the negative capacitance (NC) effect of ferroelectric materials. However, the advantages of using the NC effects alone have been utilized for perovskite ferroelectric materials, which is incompatible in complementary metal-oxide-semiconductor (CMOS) fabrication processes. In this work, a CMOS-compatible HfO2-based ferroelectric material is used for the NC + NEM system. The effects of the ferroelectric properties [i.e., remnant polarization (Pr) and coercive field (Ec)] on the NC + NEM system performance are studied in detail. The results show that the NC + NEM system can operate as a relay or a memory device depending on the Pr and Ec values. Moreover, the pull-in/out voltages of the NC + NEM system are more sensitively affected by Ec rather than Pr and decrease as Ec increases. The device design guideline with appropriate Pr and Ec values of the HfO2-based ferroelectric material is thus developed and discussed to improve the electrical characteristics of NC + NEM relay/memory devices.

The energy-delay sensitivity of a nanoelectromechanical (NEM) relay and an NEM relay with the negative capacitance of a ferroelectric capacitor (NC + NEM relay) are theoretically investigated. The energy-delay characteristics of the NC + NEM relay deteriorate compared to those of the NEM relay when its movable beam becomes shorter/thicker than the critical beam length/thickness. The energy-delay characteristics of the NC + NEM relay (vs. the NEM relay) can be improved by increasing/decreasing the movable beam length/thickness. However, the maximum length and minimum thickness of the movable electrode are specified. This is necessary to avoid stuck-on failure. This study provides guidelines for improving the switching energy-delay characteristics and the operating voltage of the NC + NEM relay (vs. the NEM relay) by optimizing the device design variables.

ML (Machine Learning)-based artificial neural network (ANN) model is proposed to estimate the LER (line edge roughness)-induced performance variation in Fin-shaped Field Effect Transistor (FinFET). For a given LER features such as rms amplitude(Δ), correlation length along x-direction (AX), and correlation length along y-direction (AY), the metrics for device performance such as on-state drive current, off-state leakage current, threshold voltage, and subthreshold swing can be computing-efficiently estimated with the ANN model.

As the physical dimensions of cell transistors in dynamic random-access memory (DRAM) have been aggressively scaled down, buried-channel-array transistors (BCATs) have been adopted in industry to suppress short channel effects and to achieve a better performance. In very aggressively scaled-down BCATs, the impact of structural variations on the electrical characteristics can be more significant than expected. Using a technology computer-aided design (TCAD) tool, the structural variations in BCAT (e.g., the aspect ratio of the BCAT recess-to-gate length, BCAT depth, junction depth, fin width, and fin fillet radius) were simulated to enable a quantitative understanding of its impact on the device characteristics, such as the input/output characteristics, threshold voltage, subthreshold swing, on-/off-current ratio, and drain-induced barrier lowering. This work paves the road for the design of a variation-robust BCAT.

In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE). The GAA-FinFET was built using the technology computer-aided design (TCAD) simulation tool, and then, its electrical characteristics were quantitatively evaluated. The electrical characteristics of the GAA-FinFET were compared to those of conventional FinFET and nano-sheet FET (NSFET) at 7 nm or 5 nm nodes. When comparing the GAA-FinFET against the FinFET, it achieved not only better SCE characteristics, but also higher on-state drive current due to its gate-all-around device structure. This helps to improve the ratio of effective drive current to off-state leakage current (i.e., Ieff/Ioff) by ~30%, resulting in an improvement in DC device performance by ~10%. When comparing the GAA-FinFET against the NSFET, it exhibited SCE characteristics that were comparable or superior thanks to its improved sub-channel leakage suppression. It turned out that the proposed GAA-FinFET (compared to conventional FinFET at the 7 nm or 5 nm nodes, or even beyond) is an attractive option for improving device performance in terms of SCE and series resistance. Furthermore, it is expected that the device structure of GAA-FinFET is very similar to that of conventional FinFET, resulting in further improvement to its electrical characteristics as a result of its gate-all-around device structure without significant modification with respect to the processing steps for conventional FinFET.

Gate configuration phase transition fully depleted silicon-on-insulator (FDSOI) metal- oxide-semiconductor field-effect transistor (MOSFET) without an external resistor is proposed using Pb(Zr0.52Ti0.48)O3 (PZT)-based threshold selector (TS). Under 1 μA compliance current condition, the PZT-based TS exhibits its threshold switching property at ~0.9 V (threshold voltage) and ~0.01 V (hold voltage) over 4 orders of current. And its off-resistance is measured as ~2.3 × 1011 Ω. The PZT-based gate configuration phase transition FDSOI MOSFET without an external resistor was fabricated by connecting the PZT-based TS to a baseline FDSOI MOSFET. It is confirmed that the fabricated external resistor-free phase transition FDSOI MOSFET can operate regardless of the aforementioned 1 μA of compliance current condition. This device has not only demonstrated the feature of ~4 mV/decade subthreshold slope at ~0.96 V of gate voltage, but it also has decreased the gate leakage current of the baseline FDSOI MOSFET by ~10 times at 0 V of gate voltage and ~320 times at 2 V of gate voltage.

A tunnel field-effect transistor with segmented channels (Seg-TFET) on a corrugated substrate is proposed. The Seg-TFET takes advantage of using three stripes and the selective contact configuration to define the direction of current, and thereby its device performance can be improved. Furthermore, the process flow of the Seg-TFET demonstrates a substantiation of the new device structure. Consequently, its current flow is simply defined by adjusting the appropriate contact configuration at metal-zero-level without any additional front-end-of-line process.

Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (ΔVth) between the top cell and bottom cell in the same string. In detail, ΔVth between the top cell and bottom cell mostly depends on the xy-scaling, but the way how ΔVth is affected is not very dependent on the stack height.

The endurance characteristic of Zr-doped HfO2 (HZO)-based metal–ferroelectric–metal (MFM) capacitors fabricated under various deposition/annealing temperatures in the atomic layer deposition (ALD) process was investigated. The chamber temperature in the ALD process was set to 120 °C, 200 °C, or 250 °C, and the annealing temperature was set to 400 °C, 500 °C, 600 °C, or 700 °C. For the given annealing temperature of 700 °C, the remnant polarization (2Pr) was 17.21 µC/cm2, 26.37 µC/cm2, and 31.8 µC/cm2 at the chamber temperatures of 120 °C, 200 °C, and 250 °C, respectively. For the given/identical annealing temperature, the largest remnant polarization (Pr) was achieved when using the chamber temperature of 250 °C. At a higher annealing temperature, the grain size in the HZO layer becomes smaller, and thereby, it enables to boost up Pr. It was observed that the endurance characteristics for the capacitors fabricated under various annealing/chamber temperatures were quite different. The different endurance characteristics are due to the oxygen and oxygen vacancies in ferroelectric films, which affects the wakeup/fatigue behaviors. However, in common, all the capacitors showed no breakdown for an externally applied pulse (up to 108 cycles of the pulse).

In this paper we demonstrate strain-dependent photoacoustic (PA) characteristics of free-standing nanocomposite transmitters that are made of carbon nanotubes (CNT) and candle soot nanoparticles (CSNP) with an elastomeric polymer matrix. We analyzed and compared PA output performances of these transmitters which are prepared first on glass substrates and then in a delaminated free-standing form for strain-dependent characterization. This confirms that the nanocomposite transmitters with lower concentration of nanoparticles exhibit more flexible and stretchable property in terms of Young’s modulus in a range of 4.08–10.57 kPa. Then, a dynamic endurance test was performed revealing that both types of transmitters are reliable with pressure amplitude variation as low as 8–15% over 100–800 stretching cycles for a strain level of 5–28% with dynamic endurance in range of 0.28–2.8%. Then, after 2000 cycles, the transmitters showed pressure amplitude variation of 6–29% (dynamic endurance range of 0.21–1.03%) at a fixed strain level of 28%. This suggests that the free-standing nanocomposite transmitters can be used as a strain sensor under a variety of environments providing robustness under repeated stretching cycles.

Abstract In this study, a near‐infrared photodetector featuring a high photoresponsivity and a short photoresponse time is demonstrated, which is fabricated on rhenium diselenide (ReSe2) with a relatively narrow bandgap (0.9–1.0 eV) compared to conventional transition‐metal dichalcogenides (TMDs). The excellent photo and temporal responses, which generally show a trade‐off relation, are achieved simultaneously by applying a p‐doping technique based on hydrochloric acid (HCl) to a selected ReSe2 region. Because the p‐doping of ReSe2 originates from the charge transfer from un‐ionized Cl molecules in the HCl to the ReSe2 surface, by adjusting the concentration of the HCl solution from 0.1 to 10 m, the doping concentration of the ReSe2 is controlled between 3.64 × 1010 and 3.61 × 1011 cm−2. Especially, the application of the selective HCl doping technique to the ReSe2 photodetector increases the photoresponsivity from 79.99 to 1.93 × 103 A W−1, and it also enhances the rise and decay times from 10.5 to 1.4 ms and from 291 to 3.1 ms, respectively, compared with the undoped ReSe2 device. The proposed selective p‐doping technique and its fundamental analysis will provide a scientific foundation for implementing high‐performance TMD‐based electronic and optoelectronic devices.

Abstract Simply including either single ferroelectric oxide layer or threshold selector, we can make conventional field effect transistor to have super steep switching characteristic, i.e., sub-60-mV/decade of subthreshold slope. One of the representative is negative capacitance FET (NCFET), in which a ferroelectric layer is added within its gate stack. The other is phase FET (i.e., negative resistance FET), in which a threshold selector is added to an electrode (e.g., source or drain) of conventional field effect transistor. Although the concept of the aforementioned two devices was presented more or less recently, numerous studies have been published. In this review paper, by reviewing the published studies over the last decade, we shall de-brief and discuss the history and the future perspectives of NCFET/phase FET, respectively. The background, experimental investigation, and future direction for developing the aforementioned two representative steep switching devices (i.e., NCFET and phase FET/negative resistance FET) are to be discussed in detail.

Although skin-like pressure sensors exhibit high sensitivity with a high performance over a wide area, they have limitations owing to the critical issue of being linear only in a narrow strain range. Various strategies have been proposed to improve the performance of soft pressure sensors, but such a nonlinearity issue still exists and the sensors are only effective within a very narrow strain range. Herein, we fabricated a highly sensitive multi-channel pressure sensor array by using a simple thermal evaporation process of conducting nanomembranes onto a stretchable substrate. A rigid-island structure capable of dissipating accumulated strain energy induced by external mechanical stimuli was adopted for the sensor. The performance of the sensor was precisely controlled by optimizing the thickness of the stretchable substrate and the number of serpentines of an Au membrane. The fabricated sensor exhibited a sensitivity of 0.675 kPa−1 in the broad pressure range of 2.3–50 kPa with linearity (~0.990), and good stability (>300 Cycles). Finally, we successfully demonstrated a mapping of pressure distribution.

In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON congeners, where the latter are known to have a good thermal budget and/or electrical characteristics, to boost the device performance under a limited thermal budget. TiN engineering for the gate-stack in the 28 nm LP HK/MG device was used to suppress the gate leakage current. Using the proposed fabrication method, the on/off current ratio (Ion/Ioff) was improved for a given target Ion, and the gate leakage current was appropriately suppressed. Comparing the process-of-record device against the 28 nm LP HK/MG device, the thickness of the electrical oxide layer in the new device was reduced by 3.1% in the case of n-type field effect transistors and by 10% for p-type field effect transistors. In addition, the reliability (e.g., bias temperature instability, hot carrier injury, and time-dependent dielectric breakdown) of the new device was evaluated, and it was observed that there was no conspicuous risk. Therefore, the HfSiO film can afford reliable performance enhancement when employed in the 28 nm LP HK/MG device with a limited thermal budget.

Abstract Improving the performance of resistive switching memories, while providing high transparency and excellent mechanical stability, has been of great interest because of the emerging need for electronic wearable devices. However, it remains a great challenge to fabricate fully flexible and transparent resistive switching memories because not enough research on flexible and transparent electrodes, for their application in resistive switching memories, has been conducted. Therefore, it has not been possible to obtain a nonvolatile memory with commercial applications. Recently, an electrode composed of a networked structure of Ag nanowires (AgNWs) embedded in a polymer, such as colorless polyimide (cPI), has been attracting increasing attention because of its high electrical, optical, and mechanical stability. However, for an intended use as a transparent electrode and substrate for resistive switching memories, it still has the crucial disadvantage of having a limited surface coverage of conductive pathways. Here, we introduce a novel approach to obtain a AgNWs/cPI composite electrode with a high figure-of-merit, mechanical stability, surface smoothness, and abundant surface coverage of conductive networks. By employing the fabricated electrodes, a flexible and transparent resistive memory could be successfully fabricated.

The negative capacitance (NC) of ferroelectric materials has paved the way for achieving sub-60-mV/decade switching feature in complementary metal-oxide-semiconductor (CMOS) field-effect transistors, by simply inserting a ferroelectric thin layer in the gate stack. However, in order to utilize the ferroelectric capacitor (as a breakthrough technique to overcome the Boltzmann limit of the device using thermionic emission process), the thickness of the ferroelectric layer should be scaled down to sub-10-nm for ease of integration with conventional CMOS logic devices. In this paper, we demonstrate an NC fin-shaped field-effect transistor (FinFET) with a 6-nm-thick HfZrO ferroelectric capacitor. The performance parameters of NC FinFET such as on-/off-state currents and subthreshold slope are compared with those of the conventional FinFET. Furthermore, a repetitive and reliable steep switching feature of the NC FinFET at various drain voltages is demonstrated.

The transient response of negative capacitance (NC) in an organic ferroelectric capacitor is experimentally investigated. To observe the transient response of the NC, a simple series network, consisting of an external series resistor and an organic ferroelectric capacitor, is built. The Landau coefficients of the organic ferroelectric capacitor were extracted from the measured polarization versus applied electric field data. A circuit level simulation was provided with the extracted parameters based on the Landau-Khalatnikov equation. To explore the impact of the RC time constant on the NC time duration in the RC series circuit, the external series resistor is altered as a tuning parameter. Also, the effect of various temperatures of the ferroelectric capacitor on the NC time duration is experimented. This paper demonstrates that either the external resistor or the ambient temperature can change the NC time duration in an organic ferroelectric capacitor.

Supercapacitors have shown great potential as a possible solution to the increasing global demand for next-generation energy storage systems. Charge repositioning is based on physical or chemical mechanisms. There are three types of supercapacitors—the electrochemical double layer, the pseudocapacitor, and a hybrid of both. Each type is further subdivided according to the material used. Herein, a detailed overview of the working mechanism as well as a new method for capacitance enhancement are presented.

Threshold voltage adjustment in threshold switching (TS) devices with HfO2/Al2O3 superlattice (by means of changing the cycle ratio of HfO2 to Al2O3 in atomic layer deposition) is investigated to implement a transparent cross-point array. TS devices with different cycle ratios (i.e., 3:1, 3:2, and 3:3) were fabricated and studied. The threshold voltage of the devices was increased from 0.9 V to 3.2 V, as the relative contents of Al2O3 layer in the superlattice were increased. At the same time, it is demonstrated that the off-resistance values of the devices were enhanced from 2.6 × 109 to 6 × 1010 Ω as the atomic layer deposition (ALD) cycle ratio of HfO2 to Al2O3 layer was adjusted from 3:1 to 3:3. However, the hold voltage and the on-current values were almost identical for the three devices. These results can be understood using the larger barrier height of Al2O3 layer than that of HfO2 layer.

Feedback field-effect transistors (FBFETs) are devices based on a positive feedback loop in which the electrons and holes in the channel region act on the energy states of the potential barrier and wall. Owing to the positive feedback phenomenon, FBFETs have an excellent subthreshold swing (~0 mV/decade at 300 K), a high on-/off current ratio (~1010), and a clear saturation region. The power consumption of both the turn-on state and turn-off state is significantly low until operation commences. In addition, the hysteresis caused by the carriers accumulated in the potential wall allows the FBFET to act as a memory device. Moreover, the power consumption of neuromorphic devices can be suppressed by ~100 times with the use of FBFETs. In this work, we analyze the device structure and operating principle of the FBFET and summarize its applications.

Culture is a key driving force in enhancing organizational performance. The results of recent studies indicate the importance of managers having the capacity to understand organizational culture and link it to organizational performance improvement. This study aims to examine the relationship between organizational culture and performance improvement in social enterprises. In the past, organizational culture was described in terms of a single dimension, but it is now understood that different cultures reflect different values and beliefs, in a seemingly contradictory manner, and can coexist within any given organization. We analyze the relationships among social enterprise networking, performance, and organizational culture, using the four organizational culture classifications of the competing values framework, which reflects recent perspectives. A survey was conducted among 100 social entrepreneurs, and latent profile analysis was applied to the data. The analytical results identify four latent profiles—namely, strong-balanced, weak-balanced, hierarchical, and group-dominant—and show that a balanced culture fosters high-level socioeconomic performance.