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The radio-frequency noise performance of FinFETs from a 60-nm gate length is investigated. It is observed that the fringing capacitance of the 3-D and multifin structure of the FinFETS is responsible for the degradation of its noise performance.

Studies have shown that SiGe heterojunction bipolar transistors (HBTs), which are optimized for high-speed performance in the forward mode of operation, have displayed an excellent performance in the reverse mode of operation. The simultaneous availability of a high-speed performance in the forward mode and a low-power performance in the reverse mode has offered additional flexibility to optimize circuit performance in terms of speed, area and power.

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and Si[O.sub.2] with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeterwave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz. Index Terms--Electrostatic discharges (ESDs), fin-shaped fieldeffect transistor (FinFET), mixed analog integrated circuits, nanotechnology.

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveal an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the key advantages over bulk MOSFETs including reduced leakage, excellent subthreshold slope, and a better voltage gain without degradation of noise or linearity.

An optimization strategy for the electrical characteristics of polysilicon emitter bipolar transistors reveals a trade off between current gain enhancement and increased 1 f noise for a range of interfacial oxide thicknesses and emitter annealing environments. The interfacial oxide has a profound influence on the 1 f noise spectrum of base current, and the polysilicon emitter interface engineering fixes the current gain in a predefined manner. The optimization technique enables fabrication of bipolar transistors of a 0.5 micrometer BiCMOS process in an LPCVD cluster.

Three different diffusion models in SiGeC layers are compared and evaluated for their implementation in the process simulation program Taurus TSUPREM-4. It is shown that the compared models are similar to each other despite the different physical approach.