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Si[N.sub.x]/Si[O.sub.2] stack-gate structures, followed by [N.sub.2]O annealing, are examined to improve the 4H-SiC metal-insulator-semiconductor (MIS) interface quality. The fabricated MISFETs with Si[N.sub.x]/Si[O.sub.2] stack-gate structure annealed in [N.sub.2]O has shown high channel mobility on the Si and C face.

The simulation and fabrication of high-voltage 4H-SiC PiN diodes with an improved junction termination structure are described. The junction termination voltage (JTE) region is optimized by device simulation and the JTE dose dependence of the breakdown voltage is compared with experimental results.

Designing and fabrication of 4H-SiC (0001) lateral MOSFETs with double reduced surface field (RESURF) structure is investigated to reduce ON resistance. It is seen that the simulated double RESURF MOSFETs with optimum doses exhibit slightly higher breakdown voltage and lower drift resistance than simulated single RESURF MOSFETs.

4H-SiC MOSFETs with various channel lengths is fabricated to investigate short-channel effects (SCEs). In the lightly doped MOSFETs, the SECs occurred even at a relatively long channel of 3-5 mum, while it was hard to observe the SCEs in the highly doped MOSFETs with a 1 mum-long channel.

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs are investigated. Device simulation is used to estimate the optimum doping concentrations (doses) of the RESURF and LDD regions to reduce the electric field crowding at the drain edge or in the gate oxide.

The impacts of carrier recombination at the surface as well as in the substrate are examined by using numerical simulation based on a diffusion equation. The simulation has shown that a very thick epilayer is needed for accurate measurement of carrier lifetimes of n-type 4H-SiC epilayers if the bulk lifetime in the epilayer is longer than several microseconds, due to the extremely short lifetimes in the substrate.

The effects of thermal oxidation on deep levels in the whole energy range of the band gap 4H-SiC are examined by using deep level transient spectroscopy. The dominant defect IP4 observed in p-type 4H-SiC after thermal oxidation is reduced by subsequent annealing in Ar, where these phenomena are explained by a model that excess interstitials are generated at the oxidizing interface, which has diffused into the bulk region.

The deep level transient spectroscopy technique is employed to explain the different deep levels that are induced by the reactive ion etching in n- and p-type 4H- SiC compounds. The concentration of the defects is shown to decrease because of thermal oxidation.

The study was conducted to measure current-voltage characteristics of Si-nanowire p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) from 101 to 396k. Findings suggest the oscillation with change in the Fermi level, resulting in the transconductance oscillation.

The wavelength range from the near band edge to 1000 nm and the temperature range from room temperature to 515 degree Celsius are utilized to study the temperature dependence of the refractive indices of GaN and AlN. The results are used for designing the GaN-based optoelectronic devices as well as wavelength-tunable distributed Bragg reflectors (DBRs) and photonic crystals actively by using the thermo-optic effect.