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Continuous scaling of transistor dimensions has been in the heart of semiconductorindustry for many years. Recently the scaling has been enabled by various performance boosters which resulted in increased processing complexity and cost, forcing the chip manufacturers to look for some alternative solutions. Monolithic 3D integration has been identified as a promising candidate for future CMOS technology nodes, as it could enable a further increasein device density through stacking tiers of older and cheaper generation transistorson top of each other. One of the major challenges faced by monolithic 3D integration is the thermal budget during upper tier fabrication since high temperature steps used in conventional CMOS processing can damage the bottom tier devices. To this respect, Ge has an advantage over Si due to its intrinsically low processing temperature. However, realizing Ge devices that provide performance and reliability comparable to Si devices is not straight forward. Gate stack formation in Ge devices is particularly challenging, as Ge lacks a stable oxide for surface passivation. In this work, gate stack solutions for Ge-based devices for monolithic 3D integration applications have been extensively studied. Low temperature Ge surface passivation with GeOx and Si-cap process has been investigated and characterized in terms of interface state density, oxide trap density and fixed charge density. GeOx has been integrated with other high-k dielectrics, suchas Al2O3, Tm2O3 and HfO2, and with the help of post deposition and forming gas treatments provided sufficient surface passivation with low interface state density. However, devices with GeOx passivation suffered from poor reliability stemming from the lack of thermal stability and high oxide trap density in GeOx layer. On the other hand, Si-cap integrated with TmSiO interfacial layer has been shown to provide both low interface trap density and oxide trap density, albeit within a narrow process window for S, Kontinuerlig nedskalning av transistorers dimensioner har varit A och O för halvledarindustrin. Den senaste nedskalningen har möjliggjorts tack vare olika prestandaförbättrare, men med dessa förbättrare har tillverkningskostnad och komplexitet ökat, vilket har lett till att chiptillverkare måste söka efter alternativa lösningar. En lovande kandidat för framtida teknologinoder är monolitisk 3D integration, där fördelen är att transistortätheten ökas genom att stapla transistorer från tidigare och billigare teknologinoder på varandra. En av de stora utmaningarna för monolitisk 3D integration är att värmebudgeten är begränsad för de övre transistorskikten eftersom att höga temperaturer, vilket krävs i konventionell transistortillverkning, kommer att förstöratransistor på de lägre skikten. Germaniumtransistorer har intrinsiskt en fördel mot kiseltransistorer i detta avseende då tillverkningen kan ske vid lägre temperatur. Dock är det utmanande att tillverka germaniumtransistorer som har prestanda och tillförlitlighet som är jämförbar med den som kiseltransistorer har. Gate-stapeltillverkningen för germaniumtransistorer är synnerligen utmanande då germanium saknar en stabil oxid som passiverar ytan. I detta arbete har lösningar till gate-tillverkningen för germaniumtransistorer för monolitisk 3D integration undersökts utförligt. Lågtemperaturprocesser för ytpassivering av germanium med germaniumoxid (GeOx) och kiselskikt (eng. Si-cap) har undersökts och karaktäriserats med avseende på tätheten på gränssnittsdefekter, fälltäthet i oxiden och fixa laddningstäthet. GeOx har integrerats tillsammans med hög-permittivitetsdielektrika, såsomaluminiumoxid (Al2O3), tuliumoxid (Tm2O3) och hafniumoxid (HfO2), och m.h.a. post-deponerings- och formgasbehandling kunde ytan passiveras tillräckligtför att uppnå en låg täthet av gränssnittsdefekter. Dock led komponenter med GeOx-passivering av dålig tillförlitlighet p.g.a. bristande termisk stabilitet och en hög fälltäthet i GeOx-skiktet, QC 20210930

Continuous scaling of transistor dimensions has been in the heart of semiconductorindustry for many years. Recently the scaling has been enabled by various performance boosters which resulted in increased processing complexity and cost, forcing the chip manufacturers to look for some alternative solutions. Monolithic 3D integration has been identified as a promising candidate for future CMOS technology nodes, as it could enable a further increasein device density through stacking tiers of older and cheaper generation transistorson top of each other. One of the major challenges faced by monolithic 3D integration is the thermal budget during upper tier fabrication since high temperature steps used in conventional CMOS processing can damage the bottom tier devices. To this respect, Ge has an advantage over Si due to its intrinsically low processing temperature. However, realizing Ge devices that provide performance and reliability comparable to Si devices is not straight forward. Gate stack formation in Ge devices is particularly challenging, as Ge lacks a stable oxide for surface passivation. In this work, gate stack solutions for Ge-based devices for monolithic 3D integration applications have been extensively studied. Low temperature Ge surface passivation with GeOx and Si-cap process has been investigated and characterized in terms of interface state density, oxide trap density and fixed charge density. GeOx has been integrated with other high-k dielectrics, suchas Al2O3, Tm2O3 and HfO2, and with the help of post deposition and forming gas treatments provided sufficient surface passivation with low interface state density. However, devices with GeOx passivation suffered from poor reliability stemming from the lack of thermal stability and high oxide trap density in GeOx layer. On the other hand, Si-cap integrated with TmSiO interfacial layer has been shown to provide both low interface trap density and oxide trap density, albeit within a narrow process window for S, Kontinuerlig nedskalning av transistorers dimensioner har varit A och O för halvledarindustrin. Den senaste nedskalningen har möjliggjorts tack vare olika prestandaförbättrare, men med dessa förbättrare har tillverkningskostnad och komplexitet ökat, vilket har lett till att chiptillverkare måste söka efter alternativa lösningar. En lovande kandidat för framtida teknologinoder är monolitisk 3D integration, där fördelen är att transistortätheten ökas genom att stapla transistorer från tidigare och billigare teknologinoder på varandra. En av de stora utmaningarna för monolitisk 3D integration är att värmebudgeten är begränsad för de övre transistorskikten eftersom att höga temperaturer, vilket krävs i konventionell transistortillverkning, kommer att förstöratransistor på de lägre skikten. Germaniumtransistorer har intrinsiskt en fördel mot kiseltransistorer i detta avseende då tillverkningen kan ske vid lägre temperatur. Dock är det utmanande att tillverka germaniumtransistorer som har prestanda och tillförlitlighet som är jämförbar med den som kiseltransistorer har. Gate-stapeltillverkningen för germaniumtransistorer är synnerligen utmanande då germanium saknar en stabil oxid som passiverar ytan. I detta arbete har lösningar till gate-tillverkningen för germaniumtransistorer för monolitisk 3D integration undersökts utförligt. Lågtemperaturprocesser för ytpassivering av germanium med germaniumoxid (GeOx) och kiselskikt (eng. Si-cap) har undersökts och karaktäriserats med avseende på tätheten på gränssnittsdefekter, fälltäthet i oxiden och fixa laddningstäthet. GeOx har integrerats tillsammans med hög-permittivitetsdielektrika, såsomaluminiumoxid (Al2O3), tuliumoxid (Tm2O3) och hafniumoxid (HfO2), och m.h.a. post-deponerings- och formgasbehandling kunde ytan passiveras tillräckligtför att uppnå en låg täthet av gränssnittsdefekter. Dock led komponenter med GeOx-passivering av dålig tillförlitlighet p.g.a. bristande termisk stabilitet och en hög fälltäthet i GeOx-skiktet, QC 20210930

The improvement of forming gas anneal (10 % H-2 in N-2) at 400 degrees C on electrical properties of Ge/GeOx/Tm2O3/HfO2 gate stacks is investigated. It is found that forming gas anneal effectively suppresses fixed charge density, oxide trap density and interface state density. Hydrogen is demonstrated to efficiently passivate the negative fixed charge density and reduce the global variability of the Hatband voltage down to 90 mV over a safer. A forming gas anneal is also found to reduce equivalent oxide thickness in scaled gate stacks., Part of proceedings: ISBN 978-1-6654-3748-6Not duplicate with DiVA 1598155QC 20220523

Continuous scaling of transistor dimensions has been in the heart of semiconductorindustry for many years. Recently the scaling has been enabled by various performance boosters which resulted in increased processing complexity and cost, forcing the chip manufacturers to look for some alternative solutions. Monolithic 3D integration has been identified as a promising candidate for future CMOS technology nodes, as it could enable a further increasein device density through stacking tiers of older and cheaper generation transistorson top of each other. One of the major challenges faced by monolithic 3D integration is the thermal budget during upper tier fabrication since high temperature steps used in conventional CMOS processing can damage the bottom tier devices. To this respect, Ge has an advantage over Si due to its intrinsically low processing temperature. However, realizing Ge devices that provide performance and reliability comparable to Si devices is not straight forward. Gate stack formation in Ge devices is particularly challenging, as Ge lacks a stable oxide for surface passivation. In this work, gate stack solutions for Ge-based devices for monolithic 3D integration applications have been extensively studied. Low temperature Ge surface passivation with GeOx and Si-cap process has been investigated and characterized in terms of interface state density, oxide trap density and fixed charge density. GeOx has been integrated with other high-k dielectrics, suchas Al2O3, Tm2O3 and HfO2, and with the help of post deposition and forming gas treatments provided sufficient surface passivation with low interface state density. However, devices with GeOx passivation suffered from poor reliability stemming from the lack of thermal stability and high oxide trap density in GeOx layer. On the other hand, Si-cap integrated with TmSiO interfacial layer has been shown to provide both low interface trap density and oxide trap density, albeit within a narrow process window for S, Kontinuerlig nedskalning av transistorers dimensioner har varit A och O för halvledarindustrin. Den senaste nedskalningen har möjliggjorts tack vare olika prestandaförbättrare, men med dessa förbättrare har tillverkningskostnad och komplexitet ökat, vilket har lett till att chiptillverkare måste söka efter alternativa lösningar. En lovande kandidat för framtida teknologinoder är monolitisk 3D integration, där fördelen är att transistortätheten ökas genom att stapla transistorer från tidigare och billigare teknologinoder på varandra. En av de stora utmaningarna för monolitisk 3D integration är att värmebudgeten är begränsad för de övre transistorskikten eftersom att höga temperaturer, vilket krävs i konventionell transistortillverkning, kommer att förstöratransistor på de lägre skikten. Germaniumtransistorer har intrinsiskt en fördel mot kiseltransistorer i detta avseende då tillverkningen kan ske vid lägre temperatur. Dock är det utmanande att tillverka germaniumtransistorer som har prestanda och tillförlitlighet som är jämförbar med den som kiseltransistorer har. Gate-stapeltillverkningen för germaniumtransistorer är synnerligen utmanande då germanium saknar en stabil oxid som passiverar ytan. I detta arbete har lösningar till gate-tillverkningen för germaniumtransistorer för monolitisk 3D integration undersökts utförligt. Lågtemperaturprocesser för ytpassivering av germanium med germaniumoxid (GeOx) och kiselskikt (eng. Si-cap) har undersökts och karaktäriserats med avseende på tätheten på gränssnittsdefekter, fälltäthet i oxiden och fixa laddningstäthet. GeOx har integrerats tillsammans med hög-permittivitetsdielektrika, såsomaluminiumoxid (Al2O3), tuliumoxid (Tm2O3) och hafniumoxid (HfO2), och m.h.a. post-deponerings- och formgasbehandling kunde ytan passiveras tillräckligtför att uppnå en låg täthet av gränssnittsdefekter. Dock led komponenter med GeOx-passivering av dålig tillförlitlighet p.g.a. bristande termisk stabilitet och en hög fälltäthet i GeOx-skiktet, QC 20210930

Continuous scaling of transistor dimensions has been in the heart of semiconductorindustry for many years. Recently the scaling has been enabled by various performance boosters which resulted in increased processing complexity and cost, forcing the chip manufacturers to look for some alternative solutions. Monolithic 3D integration has been identified as a promising candidate for future CMOS technology nodes, as it could enable a further increasein device density through stacking tiers of older and cheaper generation transistorson top of each other. One of the major challenges faced by monolithic 3D integration is the thermal budget during upper tier fabrication since high temperature steps used in conventional CMOS processing can damage the bottom tier devices. To this respect, Ge has an advantage over Si due to its intrinsically low processing temperature. However, realizing Ge devices that provide performance and reliability comparable to Si devices is not straight forward. Gate stack formation in Ge devices is particularly challenging, as Ge lacks a stable oxide for surface passivation. In this work, gate stack solutions for Ge-based devices for monolithic 3D integration applications have been extensively studied. Low temperature Ge surface passivation with GeOx and Si-cap process has been investigated and characterized in terms of interface state density, oxide trap density and fixed charge density. GeOx has been integrated with other high-k dielectrics, suchas Al2O3, Tm2O3 and HfO2, and with the help of post deposition and forming gas treatments provided sufficient surface passivation with low interface state density. However, devices with GeOx passivation suffered from poor reliability stemming from the lack of thermal stability and high oxide trap density in GeOx layer. On the other hand, Si-cap integrated with TmSiO interfacial layer has been shown to provide both low interface trap density and oxide trap density, albeit within a narrow process window for S, Kontinuerlig nedskalning av transistorers dimensioner har varit A och O för halvledarindustrin. Den senaste nedskalningen har möjliggjorts tack vare olika prestandaförbättrare, men med dessa förbättrare har tillverkningskostnad och komplexitet ökat, vilket har lett till att chiptillverkare måste söka efter alternativa lösningar. En lovande kandidat för framtida teknologinoder är monolitisk 3D integration, där fördelen är att transistortätheten ökas genom att stapla transistorer från tidigare och billigare teknologinoder på varandra. En av de stora utmaningarna för monolitisk 3D integration är att värmebudgeten är begränsad för de övre transistorskikten eftersom att höga temperaturer, vilket krävs i konventionell transistortillverkning, kommer att förstöratransistor på de lägre skikten. Germaniumtransistorer har intrinsiskt en fördel mot kiseltransistorer i detta avseende då tillverkningen kan ske vid lägre temperatur. Dock är det utmanande att tillverka germaniumtransistorer som har prestanda och tillförlitlighet som är jämförbar med den som kiseltransistorer har. Gate-stapeltillverkningen för germaniumtransistorer är synnerligen utmanande då germanium saknar en stabil oxid som passiverar ytan. I detta arbete har lösningar till gate-tillverkningen för germaniumtransistorer för monolitisk 3D integration undersökts utförligt. Lågtemperaturprocesser för ytpassivering av germanium med germaniumoxid (GeOx) och kiselskikt (eng. Si-cap) har undersökts och karaktäriserats med avseende på tätheten på gränssnittsdefekter, fälltäthet i oxiden och fixa laddningstäthet. GeOx har integrerats tillsammans med hög-permittivitetsdielektrika, såsomaluminiumoxid (Al2O3), tuliumoxid (Tm2O3) och hafniumoxid (HfO2), och m.h.a. post-deponerings- och formgasbehandling kunde ytan passiveras tillräckligtför att uppnå en låg täthet av gränssnittsdefekter. Dock led komponenter med GeOx-passivering av dålig tillförlitlighet p.g.a. bristande termisk stabilitet och en hög fälltäthet i GeOx-skiktet, QC 20210930

Continuous scaling of transistor dimensions has been in the heart of semiconductorindustry for many years. Recently the scaling has been enabled by various performance boosters which resulted in increased processing complexity and cost, forcing the chip manufacturers to look for some alternative solutions. Monolithic 3D integration has been identified as a promising candidate for future CMOS technology nodes, as it could enable a further increasein device density through stacking tiers of older and cheaper generation transistorson top of each other. One of the major challenges faced by monolithic 3D integration is the thermal budget during upper tier fabrication since high temperature steps used in conventional CMOS processing can damage the bottom tier devices. To this respect, Ge has an advantage over Si due to its intrinsically low processing temperature. However, realizing Ge devices that provide performance and reliability comparable to Si devices is not straight forward. Gate stack formation in Ge devices is particularly challenging, as Ge lacks a stable oxide for surface passivation. In this work, gate stack solutions for Ge-based devices for monolithic 3D integration applications have been extensively studied. Low temperature Ge surface passivation with GeOx and Si-cap process has been investigated and characterized in terms of interface state density, oxide trap density and fixed charge density. GeOx has been integrated with other high-k dielectrics, suchas Al2O3, Tm2O3 and HfO2, and with the help of post deposition and forming gas treatments provided sufficient surface passivation with low interface state density. However, devices with GeOx passivation suffered from poor reliability stemming from the lack of thermal stability and high oxide trap density in GeOx layer. On the other hand, Si-cap integrated with TmSiO interfacial layer has been shown to provide both low interface trap density and oxide trap density, albeit within a narrow process window for S, Kontinuerlig nedskalning av transistorers dimensioner har varit A och O för halvledarindustrin. Den senaste nedskalningen har möjliggjorts tack vare olika prestandaförbättrare, men med dessa förbättrare har tillverkningskostnad och komplexitet ökat, vilket har lett till att chiptillverkare måste söka efter alternativa lösningar. En lovande kandidat för framtida teknologinoder är monolitisk 3D integration, där fördelen är att transistortätheten ökas genom att stapla transistorer från tidigare och billigare teknologinoder på varandra. En av de stora utmaningarna för monolitisk 3D integration är att värmebudgeten är begränsad för de övre transistorskikten eftersom att höga temperaturer, vilket krävs i konventionell transistortillverkning, kommer att förstöratransistor på de lägre skikten. Germaniumtransistorer har intrinsiskt en fördel mot kiseltransistorer i detta avseende då tillverkningen kan ske vid lägre temperatur. Dock är det utmanande att tillverka germaniumtransistorer som har prestanda och tillförlitlighet som är jämförbar med den som kiseltransistorer har. Gate-stapeltillverkningen för germaniumtransistorer är synnerligen utmanande då germanium saknar en stabil oxid som passiverar ytan. I detta arbete har lösningar till gate-tillverkningen för germaniumtransistorer för monolitisk 3D integration undersökts utförligt. Lågtemperaturprocesser för ytpassivering av germanium med germaniumoxid (GeOx) och kiselskikt (eng. Si-cap) har undersökts och karaktäriserats med avseende på tätheten på gränssnittsdefekter, fälltäthet i oxiden och fixa laddningstäthet. GeOx har integrerats tillsammans med hög-permittivitetsdielektrika, såsomaluminiumoxid (Al2O3), tuliumoxid (Tm2O3) och hafniumoxid (HfO2), och m.h.a. post-deponerings- och formgasbehandling kunde ytan passiveras tillräckligtför att uppnå en låg täthet av gränssnittsdefekter. Dock led komponenter med GeOx-passivering av dålig tillförlitlighet p.g.a. bristande termisk stabilitet och en hög fälltäthet i GeOx-skiktet, QC 20210930

Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3 °C) variations of growth temperature can be detrimental to the interface state density of the gate stacks., QC 20201202

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects,defects at the SiO2/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development., Part of ISBN 9783035715798QC 20240315

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects,defects at the SiO2/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development., Part of ISBN 9783035715798QC 20240315

Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3 °C) variations of growth temperature can be detrimental to the interface state density of the gate stacks., QC 20201202

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects,defects at the SiO2/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development., Part of ISBN 9783035715798QC 20240315

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects,defects at the SiO2/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development., Part of ISBN 9783035715798QC 20240315

Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3 °C) variations of growth temperature can be detrimental to the interface state density of the gate stacks., QC 20201202

Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3 °C) variations of growth temperature can be detrimental to the interface state density of the gate stacks., QC 20201202

Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3 °C) variations of growth temperature can be detrimental to the interface state density of the gate stacks., QC 20201202

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects,defects at the SiO2/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development., Part of ISBN 9783035715798QC 20240315

State-of-the-art CMOS technology relies on the integration of multi-layer high-k/metal gate stacks in order to achieve high capacitance density while fulfilling the requirements in terms of gate leakage current density, interface state density, channel mobility, threshold voltage and reliability. Conventional SiOx/HfO2 gate dielectric stacks are capable of meeting the performance targets of current technology nodes and have been shown to possess sufficient short-term scalability, but solutions providing enhanced long-term scalability are actively researched, mostly via integration of higher-k oxides or high-k interfacial layers. This paper provides an overview of recent research efforts in this area, focusing on integration of high-k interfacial layers. We then analyze the potential scalability improvement which can be obtained through integration of thulium silicate as interfacial layer and summarize the main results supporting its applicability to future technology nodes., QC 20150605

We have investigated the annealing of fixed oxide charge and interfacial traps in MISiC strucures by means of the photo capacitance voltage technique at temperatures up to 500°C. Elevated temperature measurements show reduced hysteresis and reduced fixed oxide charge at the interface. The photo capacitance technique shows a real-time measurement at elevated temperatures, in which electrons are populated by photo energy, in a 4H-SiC MIS structure. We also confirm the reduction of fixed oxide charge at the interface by means of high temperature post deposition annealing, which occurs during the high temperature measurements., QC 20140917

High-rate spatial atomic layer deposition (ALD) enables an industrially relevant deposition of high-quality aluminum oxide (Al2O3) films for the surface passivation of silicon solar cells. We demonstrate a homogeneous surface passivation at a deposition rate of ∼30 nm/min on 15.6×15.6 cm2 silicon wafers of 10 nm thick Al 2O3 layers deposited in a novel inline spatial ALD system. The effective surface recombination velocity on n-type Czochralski-grown (Cz) silicon wafers is shown to be virtually independent of injection level. Surface recombination velocities below 2.9 cm/s and an extremely low interface state density below 8×1010 eV-1cm-2 are achieved. We demonstrate that the novel inline spatial ALD system provides the means to integrate Al2O3 passivation layers into industrial solar cells.

In this paper, we have investigated 4H-SiC p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with deposited SiO2 followed by N2O annealing. In addition to deposited oxides, dry-O2-grown oxides and N2O-grown oxides were also adopted as the gate oxides of SiC p-channel MOSFETs. The MOSFETs have been fabricated on the 4H-SiC (0001), (0001macr), (033macr8), and (112macr0) faces. The (0001) MOSFETs with deposited oxides exhibited a relatively high channel mobility of 10 cm2/V ldr s, although a mobility of 7 cm2/V ldr s was obtained in the (0001) MOSFETs with N2O-grown oxides. The channel mobility was also increased by utilizing the deposited SiO2 in the MOSFETs fabricated on nonbasal faces, although the MOSFETs on (0001macr) were not operational. Compared with the thermally grown oxides, the deposited oxides annealed in N2O are effective in improving the performance of 4H-SiC p-channel MOSFETs.

In this paper, we have investigated 4H-SiC p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with deposited SiO2 followed by N2O annealing. In addition to deposited oxides, dry-O2-grown oxides and N2O-grown oxides were also adopted as the gate oxides of SiC p-channel MOSFETs. The MOSFETs have been fabricated on the 4H-SiC (0001), (0001macr), (033macr8), and (112macr0) faces. The (0001) MOSFETs with deposited oxides exhibited a relatively high channel mobility of 10 cm2/V ldr s, although a mobility of 7 cm2/V ldr s was obtained in the (0001) MOSFETs with N2O-grown oxides. The channel mobility was also increased by utilizing the deposited SiO2 in the MOSFETs fabricated on nonbasal faces, although the MOSFETs on (0001macr) were not operational. Compared with the thermally grown oxides, the deposited oxides annealed in N2O are effective in improving the performance of 4H-SiC p-channel MOSFETs.

Metal-oxide-semiconductor capacitors based on HfO2 gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator-semiconductor interface. C-V and G-omega measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180-300 K. From the maximum of the plot G/omega vs. ln(omega) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge. The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2 x 10(11) cm(-2)eV(-1) for Al and up to (3.5-5.5) x 10(12)cm(-2)eV(-1) for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8 x 10(-17)cm(2) at 200 K for Al-HfO2-Si structure., QC 20120229

Thick (>20 μm) 4H-SiC layers in doping range of low 1015-1016 cm-3 were grown by sublimation epitaxy at a growth rate of similar to50 mum/hour. Two inch 25 μm thick layers were fabricated with standard thickness deviation of 3.77%. Effect of important process parameters on the material grade has been discussed. The Schottky diodes processed on this material sustained 900V reverse voltage at a current of 1.7 x 10-8 A, while measured on MOS capacitors the interface state density was as low as similar to6-9 x 1010 cm-2.

A significant improvement in all the important parameters of the diodes were observed by annealing in H-2 at 300 degreesC. The forward current increased from 55 mA to 100 mA at a bias voltage of 2.5 V. The reverse leakage current measured at -500 V was reduced from 3.5 x 10(-9) to 4.8 x 10(-10) Amps for a 0.5 mm diameter diode. The average value of the barrier height increased by at least 0.2 eV, measured by Capacitance-Voltage and Current-Voltage technique indicating the increase of both static and effective barrier heights. The average value of ideality factor also improved and a best value of 1.06 was obtained for the hot-wall CVD grown samples after Hz annealing. Hydrogen atoms may passivate the dangling bends at the metal-semiconductor interface and thus by saturating the dangling bonds reduce the interface state density.