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The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator’s circuit. This article presents the results of a CMOS comparator with hysteresis design – the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC. Article in Lithuanian. 65 nm KMOP technologijos histerezinio komparatoriaus projektavimas Santrauka Komparatorius yra vienas iš pagrindinių elektronikos įtaisų. Jis yra naudojamas kaip diskretinis elementas arba kaip viena iš sudėtingesnės sistemos sudedamųjų dalių. Šie įtaisai dažnai veikia elektronikos sistemose, kuriose egzistuoja ne tik informaciją nešantys bei apdorojami signalai, bet ir nepageidautini triukšmo signalai. Siekiant tokiomis sąlygomis užtikrinti patikimą ir efektyvią komparatoriaus veiką, imama taikyti histerezė. Šiame straipsnyje pateikiami TSMC 65 nm KMOP histerezinio komparatoriaus projektavimo rezultatai: aptariama principinė elektrinė schema, pateikiama suprojektuota topologija, jos kompiuterinio modeliavimo rezultatai bei išvados. Šis komparatorius bus naudojamas daugiastandarčio, daugiakanalio siųstuvo-imtuvo grandinėje, nulinio potencialo poslinkio įtampą nustatančiame, lygiagrečios architektūros analoginiame skaitmeniniame keitiklyje (ASK). Reikšminiai žodžiai:KMOP, komparatorius, histerezė, integrinis grandynas, lustas, analoginis skaitmeninis keitiklis.

Šiandien kasdienėje veikloje susiduriame su sudėtingais šiuolaikiniais elektronikos ir komunikacijų įtaisais. Jų atliekamos funkcijos vis sudėtingėja. Todėl dėstytojas mokymo procese yra priverstas duoti sudėtingas kursinių projektų užduotis, kurias studentai gali atlikti tik dirbdami komandoje. Iškyla sėkmingos komandos subūrimo problema, kuri reikalauja iš dėstytojo papildomų socialinės psichologijos, projektų valdymo ir kitų žinių. Straipsnyje pasiūlytas naujas interaktyvus ir originalus sėkmingos komandos formavimo metodas, kuris taikomas kartu su savęs vertinimo testu, sudarytu remiantis M. R. Belbin metodika. Šis metodas yra išbandytas ir jau keturis metus taikomas Vilniaus Gedimino technikos universitete, Elektronikos fakultete, vykdant grupinius kursinius projektus. Per šį laikotarpį surinkti duomenys parodė, kad sėkmingiausiai kursinius projektus vykdė komandos sudarytos iš dominuojančių koordinatoriaus, vykdytojo, užbaigėjo ir specialisto komandinių vaidmenų. Taip pat 84,4% apklausoje dalyvavusių studentų teigiamai įvertino suburtos ir projektą atlikusios komandos sinergiją. Today in daily activities, we are faced with the complex devices of modern electronics and communications. Their functions are becoming increasingly sophisticated. Therefore, the teacher in training process is forced to give challenging tasks of course project, in which students can only work as a team. There is a successful team-building problem, which requires additional knowledge of social psychology, project management and other teacher skills. The article offers a new interactive and original successful team building method, which is combined with a self-assessment test, drawn up on the basis of M. R. Belbin methodology. This method has been tested and has already applied for four years in Vilnius Gediminas Technical University Faculty of Electronics, the teamwork course projects. During this period, the collected data has shown that the most successful course projects carried out by a team formed by dominant Chairman, Implementer, Completer-Finisher, and Specialist team roles. In addition, 84.4% of the surveyed students welcomed the setting up and carried out the project team synergy.

In this paper, design and simulation results of an 8-bit 1 GS/s clock speed folding and interpolating analog-digital converter (F&I ADC) are presented. The converter for four lower bits used folding with interpolation whose coefficients respectively equal to 8 and 6, and four upper bits made using parallel comparators structure. ADC design and simulations carried out with Cadence software packages. Dynamic characteristics of the converter are presented, which shows that signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at 1 MHz input signal and 1 GS/s clock frequency is respectively equal to 49,7/54,6 dB. It is also identified effective number of bits (ENOB), which is approximately equal to 8-bit, when the input signal frequency is 1 MHz and at 500 MHz, ENOB drops to around 6-bit. After static characteristics simulation were got that the differential nonlinearity (DNL) did not exceed ±0,4 LSB and integral nonlinearity (INL) is less than ±0,6 LSB.

The investigation results of magnetic fields induced by electronic step down converters for low-voltage halogen lamps are presented. For the investigation the personal computer high definition audio system and software tools developed in the MATLAB® program package environment were used. The investigations of magnetic fields in the frequency range from 20 Hz to 48 KHz were performed.

The book describes theoretical and practical works of key technology issues for microelectronic fabrication and introduces the technology computer-aided design (TCAD) simulation tools to the reader. Examples of computer simulations provide a technically accurate introduction to advanced semiconductor manufacturing technologies: epitaxial growth, thermal oxidation, thermal diffusion and ion implantation, photolithography, etch, metallization. This publication has been produced with the financial assistance of Europe Social Fund and VGTU (Project No VP1-2.2-ŠMM-07-K-01-047). The book is a part of the project “The Essential Renewal of Undergraduates Study Programs of VGTU Electronics Faculty”.

The design aspects for low-power, low-noise CMOS charge sensitive preamplifier (CSP), that use a MOSFET transistor as a feedback resistor and leakage current compensation for use with radiation sensors are presented. Computer simulation was carried out with the SPICE simulators using the BSIM4 parameters of the IBM CMOS 90 nm and has shown to simulate CSP with the differential cascade amplifier. The advantage of this CSP design is its low-noise level, high speed and high gain with very low-power consumption of 0.5 µW for the whole preamplifier. The preamplifier has unipolar response with the peaking time of about 35...45 ns and the gain is about 60…90 mV/kē. Equivalent noise charge is less than 160 ē, when the input charge is 1…10 kē and the sensors capacitance is equal to 30 fF. These CSP’s are the most widely used for hybrid pixel sensors for high energy particle physics experiments of the charge detection and for MEMS-micromachined inertial accelerometers.

We have been simulated the submicron CMOS charge sensitive preamplifier (CSP) with the leakage current compensation circuit, which allows reducing equivalent noise charge up to 54 electrons. Simulation has been performed with SPICE simulators using the BSIMV3.3 transistors parameters of the MOSIS 0.13 µm CMOS. The value of the feedback capacitor Cfb is chosen as the CGD≈1 fF capacitance of input transistors. The feedback resistance Rfb is implemented by PMOS transistors operating in the linear region. CSP has the following main electrical parameters: the minimum of ENC is in the leakage current region -3 nA…+6 nA and equal 54…70 ē, total gain of the chain is K=41.42 mV/kē, while the peaking time is τp≈35 ns. It is a promising solution for X-ray pixel detectors.

Simulation of differential charge sensitive amplifiers (CSA) for hybrid pixel detectors on CMOS technology for high energy particle physics and for mammography, dentography has been performed with PSPICE simulator using the BSIMV3.3 parameters of the MOSIS CMOS SCN 0.24 µm. Charge sensitive preamplifier when input charge 1…30 kē and input capacitance equal 0...100 fF has the following main electrical parameters: 167...73 mV/kē gain and low power consumption 1.2 µW/channel. The preamplifier has unipolar response with peaking time about 15...79 ns. A near-Gaussian pulse shape is produced, yielding optimum signal-to-noise characteristics, and equivalent noise charge of input (ENC) less 105 ē. Thermal analysis simulated in the range T= -120…+120ºC shows changes of not more than 20 ns in the decay time and less than 10% of the output signal amplitude.

GaAs krūviui jautrių stiprintuvų modeliavimo pagal ORCAD-PSPICE programą rezultatai buvo gauti esant įvairioms KJS darbo sąlygoms, kai taškinių jutiklių talpų Cd diapazonas buvo 0,05 pF...1 pF, įėjimo signalų diapazonas Qin=1...100 fC, išėjimo apkrova RL=50, 1 k, 10 k, 100 k ir 1 MΩ; CL=2,5 pF, o aplinkos temperatūra keitėsi nuo -60 °C iki +125 °C. Šių priklausomybių analizė parodė GaAs KJS pagrindinių elektrinių parametrų gerinimo kryptis. KJS elektriniai parametrai, kai įėjimo signalas keitėsi nuo 1 iki 20 fC, stiprintuvo apkrovos varža – 1MΩ, apkrovos talpa – 2,5pF, o įėjimo talpa 0,2pF, apskaičiuoti tokie: registravimo trukmė yra lygi 8,5 ns, perdavimo koeficientas 37,7–39,4 mV/fC. Ekvivalentinis triukšmų krūvis (ENC) KJS įėjime yra mažas ir lygus 184 ē, o vartojamoji galia neviršija 1 mW. Kai KJS apkrovos varža yra maža, tai mažesni būna ir triukšmai, tačiau didesnė vartojamoji galia [...].