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We present a reconfigurable optical discriminator filter for frequency modulated microwave-photonics link applications. The filter is based on a simplified ring-assisted Mach-Zehnder interferometer configuration. It enables conversion of a highly linear frequency to amplitude modulation. Operations in a fixed bandwidth (BW) of 30 GHz and a tunable bandwidth from 10 to 30 GHz are achieved using third- and fifth-order filters. A balanced frequency discrimination architecture with electronically reconfigurable transfer characteristics is demonstrated. We measured a output-third order intercept point (OIP3) linearity improvement over that of a dual-output Mach-Zehnder.

A cantilever-based uncooled IR imager was developed utilizing a novel optical readout scheme based on inter-pixel interference. A series of small arrays (approximately 100 × 100 pixels) were fabricated using 8-in. silicon MEMS processes. The array design and process development will be discussed and initial uniformity and imaging results presented. Future challenges in developing a direct-view IR imager will be addressed.

We present arrays of electrostatically actuated piston-tip-tilt micromirrors realized using a surface micromachining 3-structural-layer polysilicon process. High fill factor, flat mirrors 120@mm in size have mechanical response in the order of 10@ms, with +/-4^o mechanical tip and tilt and 5@mm piston continuous, controllable range under 110V. The actuator design is based on four dual in-plane comb drives with 0.5@mm critical feature size and high aspect ratio. We show a modular approach to fabricate these arrays, allowing multiple array sizes (64^2 and 256^2 mirrors) and four different designs to be implemented in three DUV masks per lithography level.

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.

Compact parallel transmitters and receivers with an aggregate capacity of 107 Gb/s are built through hybrid integration of arrays of ten 100-GHz spaced directly modulated lasers, arrays of ten avalanche photodiodes, and high-index contrast silica arrayed waveguide grating multi- and demultiplexers. Unamplified transmission over 75 km of standard single-mode fiber and 155-km amplified links is demonstrated in the C-band, by using a modulation format based on spectral offset filtering and electronic dispersion compensation.

We report on a 10 × 11.1-Gb/s optoelectronic multiwavelength receiver with 100-GHz channel spacing and 14-dBm per-channel sensitivity. The device uses hybrid integration of separately optimized elements to achieve high optical sensitivity. A novel micromachined optical turning mirror has been developed to simplify the fabrication and assembly of the receiver.

We present a 75km-reach 100Gb/s DWDM transmitter based on a fully passive, hybrid assembly of a 10x10Gb/s laser array with a low-loss SiO2 AWG, and its optimization for thermal management, low cost and high yield.

We present a 35nm tunable laser by hybrid integration between a reflective semiconductor optical amplifier and an external cavity based on silica ring resonators and a Mach-Zehnder interferometer. We demonstrate a record low 2kHz line width.

We demonstrate free-space space-division-multiplexing (SDM) with 15 orbital angular momentum (OAM) states using a three-dimensional (3D) photonic integrated circuit (PIC). The hybrid device consists of a silica planar lightwave circuit (PLC) coupled to a 3D waveguide circuit to multiplex/demultiplex OAM states. The low excess loss hybrid device is used in individual and two simultaneous OAM states multiplexing and demultiplexing link experiments with a 20 Gb/s, 1.67 b/s/Hz quadrature phase shift keyed (QPSK) signal, which shows error-free performance for 379,960 tested bits for all OAM states.

We propose an optical interleaver using an arrayed waveguide grating-lens-grating cascade and a 3-dB coupler. It has a narrow channel spacing, high-order Gaussian passbands, and low chromatic dispersion. We demonstrate a 16.7-GHz version for spectrally efficient wavelength-division-multiplexed systems.

In this paper, we tailor the evanescent field coupling between two metal layers with subwavelength slit arrays and created a half-wave plate that imparts a half-wave phase delay to one component of linear polarization. The polarization of linearly polarized light at 1.55 μm wavelength can be rotated by up to 90 degrees, with polarization extinction ratio exceeding 22 dB. One advantage of this device over conventional polarization rotators is that the wavelength of operation can be chosen by fabricating subwavelength slit arrays with different parameters. Moreover, future devices can be designed to be mechanically tunable by suspending one of the metal plates. Nanomechanical motion between the two metal layers changes the evanescent field coupling between them, allowing real time control of the polarization of the transmitted light.

We demonstrate a low-loss hybrid-integrated device based on a silica planar lightwave circuit (PLC) coupled to a 3-D photonic circuit that efficiently generates and multiplexes 15 optical orbital angular momentum (OAM) modes in free space.

We show error-free 10GBd DQPSK data transmission performance using orbital angular momentum (OAM) modes that are multiplexed and demultiplexed by a low-loss, hybrid-integrated device based on a silica planar lightwave circuit (PLC) coupled to a 3-D photonic integrated circuit.

We report our experimental results for linear analog optical links that use phase or frequency modulation and optical discrimination. The discriminators are based on two architectures: a cascaded MZI FIR lattice filter and a ring assisted MZI (RAMZI) IIR filter. For both types of discriminators, we demonstrate > 6 dB improvement in the link's third-order output intercept point (OIP3) over a MZM link. We show that the links have low second-order distortion when using balanced detection. Using high optical power, we demonstrate an OIP3 of 39.2 dBm. We also demonstrate 4.3dB improvement in signal compression.

A phase modulated (PM) microwave photonic link (MPL) with linearity improvement is presented. The link demodulates the PM using a phase discriminator based on a dynamically tunable, integrated, sixth-order optical lattice filter in planar lightwave circuit (PLC) technology. The linearity of the demodulation process is optimized by using electrical spectrum monitoring and a feedback algorithm to automatically choose the filter coefficients. For a 2 GHz modulation frequency, the link achieves a 6.7 dB improvement in the third-order output intercept point (OIP3) for intermodulation distortion (IMD) over a Mach-Zehnder interferometer (MZI).

International audience; We measure the Casimir force between a gold sphere and a silicon plate with nanoscale, rectangular corrugations with depth comparable to the separation between the surfaces. In the proximity force approximation (PFA), both the top and bottom surfaces of the corrugations contribute to the force, leading to a distance dependence that is distinct from a flat surface. The measured Casimir force is found to deviate from the PFA by up to 15%, in good agreement with calculations based on scattering theory that includes both geometry effects and the optical properties of the material.

We measure the transmission of IR radiation through double-layer metal films with periodic arrays of subwavelength holes. When the two metal films are placed in sufficiently close proximity, two types of transmission resonances emerge. For the surface plasmon mode, the electromagnetic field is concentrated on the outer surface of the entire metallic layer stack. In contrast, for the guided mode, the field is confined to the gap between the two metal layers. Our measurements indicate that, as the two layers are laterally shifted from perfect alignment, the peak transmission frequency of the guided mode decreases significantly, while that of the surface plasmon mode remains largely unchanged, in agreement with numerical calculations.

We review the fabrication process of a recently introduced phase only MEMS based spatial light modulators for maskless lithography. A brief description of this device is presented. The physical properties of its structural layers and the difficulties encountered during its fabrication process are described in detail.

We have fabricated and tested sub-50nm gate length nMOSFETs with fT up to 290GHz to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. We have also developed an accurate, high frequency (1 -50GHz) model suitable for integration with digital CMOS

We are exploring the feasibility of sequencing a single molecule of DNA using a revolutionary type of silicon integrated circuit that incorporates an on-chip nanopore mechanism with a molecular trap. The essential component is a single, nanometer-diameter pore in a robust, nanometer-thick membrane formed from a Metal Oxide Semiconductor (MOS) capacitor. To sequence the molecule, the voltage induced by the dipole moment associated with each base is measured using the electrodes on the capacitor as the DNA translocates through the pore.

We describe the design, fabrication and dynamics of a two dimensional array of MEMS piston mirrors that fulfil the requirements needed to modulate deep ultraviolet radiation for mask pattern generation

We characterize a 200 GHz channel grid, wavelength-selective 4/spl times/1 switch with wide/flat passbands and low chromatic dispersion (|CD

We have fabricated and demonstrated a new device called the Vertical Replacement-Gate (VRG) MOSFET. This is the first MOSFET ever built that combines (1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and (2) a high-quality gate oxide grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes a self-aligned S/D formed by solid source diffusion (SSD) and small parasitic overlap, junction, and S/D capacitances. The drive current per /spl mu/m of coded width is significantly higher than that of advanced planar MOSFETs because each rectangular device pillar (with a thickness of minimum lithographic dimension) contains two MOSFETs driving in parallel. All of this is achieved using current manufacturing methods, materials, and tools, and competitive devices with 50-nm gate lengths (L/sub G/) have been demonstrated without advanced lithography.

We report a new super self-aligned graded SiGe base transistor that uses high energy implantation, rather than epitaxial growth, to form the sub-collector region. This new inexpensive process yields a device with f/sub T/ of 52 GHz and f/sub max/ of 70 GHz with the addition of only 4 lithography levels over our 0.25 /spl mu/m CMOS technology without any changes to the existing process steps. Also, we demonstrate 4:1 multiplexer and 1:4 demultiplexer circuits using this technology that show excellent performance at 10 Gbit/s.

We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (

Multiple t/sub OX/ is thoroughly investigated for nitrogen-implanted gate oxides with the optimization of Q/sub BD/ and a demonstration of 2 GHz counters. Furnace growth at 800/spl deg/C, 850/spl deg/C, and 900/spl deg/C is compared with rapid-thermal-oxidation (RTO) at 1050/spl deg/C. A wide range of reduced growth rate, 20% to 80%, is achieved that meets the SIA road-map for the next few generations of the CMOS technology. Optimization of charge-to-breakdown (Q/sub BD/) is achieved through investigation of the nitrogen distribution profile in the oxide that is affected by the growth temperature, nitrogen implant dose, and post-oxidation anneals. 10/sup 15//cm/sup 2/ nitrogen dose results in a higher Q/sub BD/ as well as a tighter tail distribution of Q/sub BD/ than 5/spl times/10/sup 14//cm/sup 2/ nitrogen dose. The tight distribution of Q/sub BD/ is important for yield improvement. If the oxide is either grown or annealed at 900/spl deg/C, Q/sub BD/ is as good as the Q/sub BD/ of regular oxide without nitrogen. As an example of integration, 0.18-/spl mu/m CMOS devices with dual gate oxides of 3 nm and 4 nm are fabricated and characterized at 1.5, 1.8, and 2.5 V. Performance of divide-by-3 counters is evaluated with the consideration of parasitic RC delays, and the results are superior to the most recently published data. At room temperatures, the maximum toggle frequency (f/sub T/) is higher than 2 GHz for both 1.8 and 2.5 V operation, with a power dissipation of 3.4 /spl mu/W at 85/spl deg/C. To further reduce the power dissipation to 0.08 /spl mu/W, 1.5-V operation gives 1-GHz f/sub T/ also at 85/spl deg/C.

Summary form only given. We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget for gate activation, made possible by short diffusion distances, not only reduces dopant lateral diffusion in the gates but also in the device channel regions. Moreover, the process allows the use of thinner gate oxides and shallower junctions and improves the control of L/sub eff/.

In this work, we first establish the relationship between corner leakage and corner rounding through device simulation. Then, we demonstrate a novel method to produce corner rounding, using a post-CMP, high temperature re-oxidation process (HTR-STI). A semi-empirical model correlating rounding with re-oxidation and nitride mask thickness is derived from mechanical studies. Finally, we show the electrical properties of devices with HTR-STI for the 0.18 /spl mu/m technology.

A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications. Critical process features include 248 nm DUV lithography on all levels, profiled twin tubs by high energy implantation (HEI), dual TiN/polysilicon gates with low resistance on minimum size lines, rapid thermal (RT) N/sub 2/O grown 5.5 nm gate dielectrics, and planarized multi-level interconnect. Transistors are demonstrated with symmetric thresholds and excellent short-channel characteristics down to channel lengths of 0.18 /spl mu/m. Fabricated circuits operate down to

We have investigated a new class of high K gate dielectric materials, Si-doped aluminates. These dielectrics, with TiN gates, can withstand high temperature CMOS processing and therefore do not require replacement gate technology. In this paper we focus on Si-doped zirconium aluminate (Zr-Al-Si-O), with K/spl sim/20. With the TiN gate stack subjected to the standard CMOS thermal budget, we have scaled this dielectric to t/sub eq//spl sim/1.2 nm with leakage current 15) may be viable alternate gate dielectrics.

We present the SALVO CMOS process, first device data and simulation study with the following features: (1) self-aligned local channel implants for SCE reduction; (2) sub-50 nm fabrication using only current production tools; (3) replacement gate with dual-polysilicon for low V/sub T/; (4) low aspect-ratio gates with CD insensitive to lithography and etch profile variability. The first demonstration of SALVO process shows it is a viable candidate for future ULSI CMOS production, in view of its versatility, controllability and compatibility.

We have integrated HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer chemical vapor deposition (ALD) with poly-Si gate electrodes in the vertical replacement-gate (VRG) MOSFET geometry. These transistors are among the first reported with ALD HfO/sub 2/ gate dielectrics, and have HfO/sub 2/ target equivalent oxide thicknesses (tEOT's) down to 13 /spl Aring/. The poly-crystalline HfO/sub 2/ films in these VRG nMOSFETs exhibit extremely low gate leakage (GL) current densities of J/sub G/ /spl sim/ 10/sup -7/ A/cm/sup 2/ at V/sub G/-V/sub T,Long/ = 0.6 V for 15 /spl Aring/ tEOT devices. This indicates that amorphous gate dielectrics may not be necessary to meet GL requirements. HfO/sub 2/ devices with 50 nm gate length L/sub G/ exhibit drive currents [normalized by the coded width W/sub C/] of 490 /spl mu/A//spl mu/m for 1 V operation (overdrive V/sub GS/-V/sub T/ = 0.6 V) with good short-channel performance. These results demonstrate that ALD is compatible with the demanding VRG geometry, thereby illustrating that it should be well-suited to essentially any novel device structure built with Si-compatible materials.

The need for sub-100 nm semiconductor devices has driven our industry to develop new resists, exposure tools (248 nm, 193 nm, extreme ultraviolet, SCALPEL, etc.), mask technologies, and processing procedures. An enormous amount of research has gone into every aspect of the semiconductor device fabrication process and new techniques to further reduce the critical dimensions need to be investigated. The work that is reported on in this article identifies a process that is referred to as liquid ashing. Liquid ashing is a novel approach to linewidth reduction of resist features patterned with positive 248 nm deep-ultraviolet (DUV) resists. The lashing process reduces linewidth through the use of a second wet development step. This process is isotropic and can be continued once started. A bake prior to the second development improves process control. Various types of phase-shifted patterns have been measured and evaluated to determine the effectiveness of this process. This process has been exercised using different resists, different developers, and several different integrated circuit (IC) test patterns. Linewidth reduction using liquid ashing is controllable, does not increase linewidth variations, and can be accomplished using existing equipment. The process was evaluated with IC test patterns that were printed using attenuated phase shifted mask technology generated photo masks and conventional DUV processes. Scanning electron microscopy was used to obtain critical dimension data and cross-sectional information. Features, ranging from 120 to 280 nm in size were reduced by 60 nm at a controllable rate of approximately 1.25 nm/s. Transistor gates as small as 60 nm have been formed in 248 nm DUV resist and successfully transferred while maintaining >85° wall profile.

To demonstrate the effectiveness of alternating aperture phase shift lithography for integrated circuit manufacturing, a demonstration device was designed and processed. A 2 million transistor integrated circuit was processed with a phase shifted gate level using 248 nm wavelength lithography. The lithographic results were confirmed by careful feature size measurements throughout the process sequence and finally by the performance of the devices themselves. Gate lengths were reduced from 240 to 120 nm, resulting in fully functional chips with 100 MHz circuit speed at 1.0 V operation, more than a two-fold speed improvement and a record for communication circuits of this type at a low supply voltage.

We report on progress toward scaling both N-metal–oxide–semiconductor (MOS) and P-metal–oxide–semiconductor MOS transistors to a gate length of 30 nm. We describe lithography and pattern transfer results that are suitable to meet this goal. Scanning capacitance microscopy is used to determine the effective channel lengths and source drain junction depths on cross-sectioned devices to optimize the fabrication process. We present interim electrical results obtained for high performance, down to Lg=57 nm, N-MOS and P-MOS transistors made using this process. We have also used a device simulation program to predict subthreshold current for N-MOS transistors with gate lengths from 40 to 26 nm. The simulation provides insights into the effects of critical dimension control and edge roughness on leakage current, and has implications for extending large scale integration of MOS technology beyond 50 nm.

Results are described for a gate level technology module developed to produce metal–oxide–semiconductor transistors with physical gate lengths of 70 nm and below. Lithography is performed by direct write e-beam lithography (EBL) using a thermal field-emission EBL system in SAL 601 resist. Critical dimension (CD) control, as measured by several methods, is found to depend not only on dose control but also on writing parameters such as pixel spacing. The pattern transfer using a silicon dioxide hard mask is shown to exhibit a trade-off between anisotropy and selectivity. Transmission electron microscopy cross sections reveal that two atomic layers are removed even when the gate oxide stopping layer is completely intact. We report results for gate lengths down to 60 nm with edge roughness on the order of 5 nm, within the acceptable limits for threshold requirements, while stopping the etch process on oxides as thin as 1.2 nm.

We modified a polycide gate etching chamber of an Applied Materials Precision 5000 platform to accept a commercially available Prototech 150-mm-diam helical resonator plasma source to extend the utility of this proven manufacturing platform to 0.25 μm technology and beyond. We successfully demonstrated the use of the helical resonator on the Precision 5000 platform to etch WSix/α-Si gate stacks using a multistep process. At low pressures (

We propose a novel technique for reducing substrate reflections in 248 nm deep ultraviolet (DUV) lithography. The method we have developed utilizes a multilayer scheme comprised of layers of silicon rich oxide. Deposition of the film stack is carried out on a production ready PE‐CVD tool in one continuous operation. The combining of multiple layers allows a gradual change in absorption thereby minimizing the reflection coefficient at the resist/ARC interface. The method of operation of these films is one of total absorption rather than the more common destructive interference method of a single layer film which relies on very tight thickness control. Absorption of the combined films is high enough to be effective on even the most highly reflective substrates such as aluminum. Furthermore, this technique does not require the ARC films to be tuned in their optical constants to accommodate the underlying substrate. We have successfully patterned wafers with feature sizes as small as 200 nm with no appreciable change in line width due to the underlying topography. The multilayer ARC system has been successfully integrated into the gate level of a 0.25 μm design rule device with excellent results. A description of the films used, their optical properties, and results from experimental data, as well as numerical simulations, will be reported.

In situ optical emission and ellipsometry are used to control the etching of titanium nitride/polysilicon gate stacks deposited on 70 A gate oxide patterned with 0.25–0.35 μm design rules. Multistep recipes using various chemistries are developed and optimized with a low pressure, high plasma density helicon source in which the goal is to obtain stringent profile control, and high selectivity to the gate oxide. The characteristic real‐time optical emission and ellipsometry traces are used as a reference to evaluate reproducibility and to compare the etching rates as a function of the different processing conditions. Optical emission and ellipsometry appear crucial for the rapid development of a multistep etching sequence using various chemistries. Complementary post‐process diagnostics using a spectral reflectometer for film thickness measurements and scanning electron microscopy for quantification of profile control are also presented.

Etching of polysilicon features using a helical resonator plasma source is evaluated. Performance metrics consist of etching rate, etching rate uniformity, and profile control using HBr/O2–He gas‐phase chemistry. The effect of source power, rf‐bias power, and reactor pressure on etching rate and uniformity is examined using a response surface experiment. Feature profile control is determined by examining nested and isolated lines and trenches using oxide mask/polysilicon/oxide structures. Good uniformity and vertical profiles are obtained at low reactor pressures, high source power, and rf‐bias between 50 and 60 W. The operating point for best uniformity is at 3.5 mTorr, 3000 W source power, and 53 W rf‐bias power. At this point, the etching rate is 3700 A/min and the nonuniformity is less than 1.0%, over 125‐mm‐diam wafers. Radial profiles of electron temperature and ion density near the wafer surface are presented as a function of source power, rf‐bias power, and reactor pressure. The ion density was fo...

The effect of plasma induced damage on device yields becomes increasingly crucial as gate oxide thicknesses approach the 50–70 A range for quarter micron design rules. To quantify plasma induced damage for new low pressure, high density plasma sources, inductively coupled carrier lifetime and photoluminescence are measured. Also, UV‐visible spectroscopic ellipsometry is used to closely examine the wafer surface both during and after plasma exposure. This study is part of an ongoing research program that compares the etching performance of two commercially available, advanced plasma sources: a Lucas Labs helicon and a Wavemat multipole electron cyclotron resonance source. For n‐type and p‐type, nominally 100 μs lifetime wafers, plasma exposure in both sources under optimum polysilicon overetch conditions results in a degradation of carrier lifetimes of less than 5% for unprotected versus oxide protected crystalline silicon. For wafers with an initial carrier lifetime of 400 μs, exposure to plasmas in both ...

We demonstrate orbital angular momentum state conversion using two 3D photonic integrated circuits for free-space communication of 20-Gb/s QPSK signals. Different combinations of OAM states show error-free performance with 379,960 bits tested.

A 72/spl times/72 wavelength-selective crossconnect switch, that is scalable to 1296/spl times/1296 with current technology, is presented. Silica-on-silicon wavelength multiplexers with integrated monitoring taps and a MEMS micromirror array were assembled in a hybrid 3D beam steering crossconnect having 20 dB insertion loss, 100 GHz channel spacing and 30 GHz passbands.

We present arrays of electrostatically actuated 64times64 piston-tip-tilt micromirrors realized using a surface micromachining 3-structural-layer polysilicon process. High fill factor, flat mirrors 120 mum in size have mechanical response in the order of 10 mus, with plusmn4 mechanical tip and tilt and 5 mum piston continuous, controllable range under 110 V. The actuator design is based on four dual in-plane comb drives with 0.5 mum critical features size