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Resistive random access memory (RRAM) based computing-in-memory (CIM) is attractive for edge artificial intelligence (AI) applications, thanks to its excellent energy efficiency, compactness and high parallelism in matrix vector multiplication (MatVec) operations. However, existing RRAM-based CIM designs often require complex programming scheme to precisely control the RRAM cells to reach the desired resistance states so that the neural network classification accuracy is maintained. This leads to large area and energy overhead as well as low RRAM area utilization. Hence, compact RRAMbased CIM with simple pulse-based programming scheme is thus more desirable. To achieve this, we propose a chip-in-the-loop training approach to compensate for the network performance drop due to the stochastic behavior of the RRAM cells. Note that, although the target RRAM cell here is a two-state RRAM (i.e binary, having only high and low resistance states), their inherent analog resistance values are used in the CIM operation. Our experiment using a 4-layer fully-connected binary neural network (BNN) showed that after retraining, the RRAM-based network accuracy can be recovered, regardless of the RRAM resistance distribution and RHRS/RLRS resistance ratio. Agency for Science, Technology and Research (A*STAR) Submitted/Accepted version We thank the Programmatic grant no. A1687b0033, Singapore RIE 2020, AME domain.

Mel frequency cepstral coefficient (MFCC) features are widely used in applications such as keyword spotting, bearing fault detection and heart sound classification. This work proposes a low power MFCC engine that enables its use for battery-powered edge applications. Three hardware algorithm co-optimizations were adopted to achieve energy efficient MFCC hardware implementation. The approximated MFCC features due to the optimizations still allows good accuracy when deployed in several applications such as keyword spotting and bearing fault detection, reporting negligible accuracy drop of 1.5%. The proposed MFCC hardware consumes only 128nW at 0.3V supply and occupies only 0.08mm2 in 40nm CMOS technology, which are 5x and 2.75x power and area reduction respectively when compared to the prior arts. National Research Foundation (NRF) Submitted/Accepted version We thank the Programmatic grant no. A1687b0033, Singapore RIE 2020, AME domain.

In this work, we propose a novel hybrid method for scene text detection namely Correlation Propagation Network (CPN). It is an end-to-end trainable framework engined by advanced Convolutional Neural Networks. Our CPN predicts text objects according to both top-down observations and the bottom-up cues. Multiple candidate boxes are assembled by a spatial communication mechanism call Correlation Propagation (CP). The extracted spatial features by CNN are regarded as node features in a latticed graph and Correlation Propagation algorithm runs distributively on each node to update the hypothesis of corresponding object centers. The CP process can flexibly handle scale-varying and rotated text objects without using predefined bounding box templates. Benefit from its distributive nature, CPN is computationally efficient and enjoys a high level of parallelism. Moreover, we introduce deformable convolution to the backbone network to enhance the adaptability to long texts. The evaluation on public benchmarks shows that the proposed method achieves state-of-art performance, and it significantly outperforms the existing methods for handling multi-scale and multi-oriented text objects with much lower computation cost.

The joint Viterbi detector decoder (JVDD) was recently proposed as an alternative to iterative detector/decoder systems (also known as turbo equalizers) used in communication applications today. Despite being conditionally optimal over coded additive white Gaussian noise (AWGN)/inter-symbol interference (ISI) channels, the JVDD suffers from an exponential growth in the number of survivors when used with existing codes such as random low-density parity check (LDPC) codes. This paper proposes a class of JVDD codes designed for the JVDD which mitigate this undesirable trait. This class of codes consists of 4 code designs — 1) fixed row weight, 2) fixed column weight, 3) proportionate row weight and 4) proportionate column weight. While the proposed JVDD codes do effectively bring about a reduction in complexity and enhance the performance of the JVDD, the design parameters of these codes require optimization. In this paper, a design of experiment (DOE) technique that employs the response surface methodology (RSM) is used as a tool to optimize the parameters of each of the proposed codes.

A cascade distributed amplifier (DA) is designed and analyzed in this letter. The proposed DA is fabricated in 0.13 μm SiGe HBTs process and patterned ground micro-strips are deployed for the design of distributed inductors to achieve high-Q in the transmission line (TL). In addition, negative resistors and capacitors are used to widen the bandwidth. Gain boosting techniques are also used to ensure gain flatness throughout the band. The fabricated DA achieves an average gain of 17.5 dB and 14.5 dB gain at 110 GHz. 7.5 and 2.7 dBm saturated output power are obtained at 50 and 100 GHz, respectively. The total chip size is 0.8 mm × 1.8 mm, including the bond pads.

A low power, 5-Mb/s fully integrated body channel Frequency Shift Keying (FSK) transmitter using the human body as a signal transmission medium is designed for medical data transmission in body area network. The FSK transmitter has a 9-bit digitally controlled injection locked ring oscillator in place of the power consuming Phase-Locked Loop (PLL) to achieve low energy consumption and ultra wide-band tuning range. 30 MHz to 120 MHz band is used by the body channel transmitter to overcome the body antenna effect. A multiple injection lock modulation scheme is proposed for the 5-Mb/s FSK. The chip is implemented with a 0.18-μm CMOS process using 1.2-V supply. When working at 5 Mb/s, the transmitter core power consumption is only 146.64 μW.

This letter presents a temperature compensated oscillator for clock generation across a wide temperature range. The proposed technique deploys the characteristics of the constant-biased varactors to nullify the overall oscillator's temperature coefficient (TC), thereby reducing the temperature drift effect on the oscillator frequency output. Fabricated on a CMOS technology, the proposed 2.09 GHz-gm-LC oscillator sees a mere frequency drift from -20°C to 120°C. The oscillator consumes 10.9 mW at 1.4 V supply, with phase noise of -119.4 dBc/Hz at a 1 MHz offset. The demonstrated technique is useful for providing accurate clock for a variety of applications, including those operating in harsh environment. ASTAR (Agency for Sci., Tech. and Research, S’pore) Accepted version

This paper articulates a novel oscillator design that can provide stable frequency operation over a wide temperature range with self-calibration technique. A simple ring oscillator is implemented to sense the temperature variation, and some digital circuits tune the output frequency according to the sensing outcomes. Simulation results show that the circuit can generate a stable frequency of 13.8MHz. The power consumption of the whole system is only 52.8µW. The temperature coefficient is less than ±0.4% ranging from -55 to 125 ◦C in the worst process corner whereas the supply voltage is ultra-low at 0.6V. Accepted version

This paper presents a 330 GHz frequency modulator. 82.5 GHz input signal is modulated by a Gilbert cell and the modulated signal is converted to 330 GHz via two cascaded push-push frequency doublers. Stacked push-push configuration is used for enhancing the output power at 330 GHz and passive Baluns with asymmetrical grounding stub is deployed to improve the power efficiency. The proposed design is fabricated using 0.13-μm SiGe BiCMOS process. The total chip area is 0.95 mm×1 mm. The DC consumption is 42.5 mW including the buffers and the input power of the 82.5 GHz carrier is −8 dBm. The proposed design demonstrates good input/output return losses through on-chip measurement and the modulated output spectrums are obtained at 330 GHz.

This paper presents the principle and design of an SOI-CMOS low noise chopper amplifier for electronic data acquisition system in down-hole-drilling application that operates at the high temperature (>170 oC) regime. The chopper amplifier is designed to have three-stages where the first stage is a folded cascade. A commercially available 1-μm SOI-CMOS technology was chosen. Simulations showed that the input-referred noise of the chopper amplifier is about 25.6 nV/sqrt(Hz) at 700 Hz with a total current consumption of 5.496 mA. Measurements proved that the chopper amplifier is able to work up to 300 oC.

This paper presents a resonant-based read-out circuit for capacitive pressure sensors. The proposed read-out circuit consists of an LC oscillator and a counter. The circuit detects the capacitance changes of a capacitive pressure sensor by means of frequency shifts from its nominal operation frequency. The proposed circuit is designed in 0.18m CMOS with an estimated power consumption of 43.1mW. Simulation results show that the circuit has a capacitive resolution of 8.06kHz/fF, which enables it for high resolution pressure detection., {"references":["","R. Puers, \"Capacitive sensors: When and how to use them,\" Sens.\nActuators A, Phys., vol. 37/38, pp. 93–105, Jun.–Aug. 1993.","O. Brand, \"Microsensor integration into systems-on-chip,\" Proc. IEEE,\nvol. 94, no. 6, pp. 1160–1176, Jun. 2006.","Dong-Yong Shin, Hyunjoong Lee, and Suhwan Kim, \"A delta–Sigma\ninterface circuit for capacitive sensors with an automatically calibrated\nzero point,\" IEEE Transactions on Circuits and Systems II: Express\nBriefs, vol. 58, pp. 90–94 , Feb. 2011.","Dong-Yong Shin, Hyunjoong Lee, and Suhwan Kim, \"Improving the\naccuracy of capacitance-to-frequency converter by accumulating\nresidual charges,\" IEEE Transactions on Instrumentation and\nMeasurement, vol. 60, pp. 3950–3955, Dec. 2011.","Zhichao Tan, et.al, \"A 1.8V 11μW CMOS smart humidity sensor for\nRFID sensing applications,\" Proc. IEEE Asian Solid State Circuits\nConference, pp. 105–108, Nov. 2011.","J. A. Geen, S. J. Sherman, J. F. Chang, S. R. Lewis, \"Single chip surface\nmicromachined integrated gyroscope with 50°/h Allan deviation,\" IEEE\nJ. of Solid-State Circuits, vol. 37, Dec. 2002, pp.1860–1866.","S.J. Sherman, et.al., \"Low cost monolithic accelerometer\", Dig. VLSI\nCircuits Symp., June 1992, pp. 34–35.","K. Chau, S.R. Lewis, Y, Zhao, R. T. Howe, S.F. Bart, and R.G.\nMarcheselli, \"An integrated force-balanced capacitive accelerometer for\nlow-g applications,\" 1995 IEEE Conf. on Solid-State Sensors &\nActuators, June 1995, pp. 593–596.","J. Wu, G.K. Fedder, L.R. Carley, \"A low-noise low-offset capacitive\nsensing amplifier for a 50-g/Hz monolithic CMOS MEMS\naccelerometer\", IEEE J. of Solid-State Circuits, vol. 39, May 2004, pp.\n722–730.\n[10] C. T. Chiang, C. S. Wang and Y. C. Huang, \"A CMOS integrated\ncapacitance-to-frequency converter with digital compensation circuit\ndesigned for sensor interface applications,\" Proc. IEEE Sensors, pp. 954\n–957, Oct. 2007.\n[11] W. Bracke, P. Merken, R. Puers and C. V. Hoof, \"Ultra-low-power\ninterface chip for autonomous capacitive sensor systems,\" IEEE Trans.\nCircuits Syst. I, Reg. Papers, vol. 54, no. 1, pp. 130–140, Jan. 2007.\n[12] Hans Danneels, Kristof Coddens and Georges Gielen, \"A fully-digital,\n0.3V, 270 nW capacitive sensor interface without external references,\"\nProc. Of the ESSCIRC, pp. 287–290, Sep. 2011.\n[13] Efstathios D. Kyriakis-Bitzaros, et. al., \"A reconfigurable multichannel\ncapacitive sensor array interface,\" IEEE Transactions on\nInstrumentation and Measurement, vol. 60, pp. 3214–3221, Sep. 2011.\n[14] Daheng Yin, Zunqiao Zhang, and Janwen Li \"A simples\nwitchedcapacitor-based capacitance-to-frequency converter\" Analog\nIntegrated Circuit and Signal Processing 1, pp.353–361, 1991.\n[15] Krummenacher, \"A high-resolution capacitance-tofrequency converter,\"\nIEEE Journal of Solid-State Circuits, vol. sc–20, no. 3, pp. 666–670,\nJun. 1985.\n[16] Cheng-Ta Chiang, Chi-Shen Wang, and Yu-Chung Huang \" A CMOS\nintegrated capacitance-to-frequency converter with digital compensation\ncircuit designed for sensor interface applications\", in Proc. of IEEE\nSensors 2007, pp 954–957, 2007.\n[17] Raúl Aragonés, et. al., \"A capacitance-to-frequency converters\ncomparison for a frequency acquisition platform,\" in Proc. of IEEE\nSensors 2007, pp 1431–1436, 2010."]}

This brief presents a high-voltage (HV) transducer driver to fulfill the requirement of the proposed high-data-rate down-hole acoustic telemetry system. The driver is targeted to drive a stack of piezoelectric disks modeled as a capacitive load of 0.3 μF and across a broadband from 600 Hz to 1.2 kHz. To ensure stability, the driver is designed as an open-loop system, comprising a dead-time controller, level shifters, gate drivers, and power MOSFETs. The driver is fabricated using the 1.0- μm silicon-on-insulator CMOS process and its performance is investigated up to 260 °C, far beyond the specified process limit of 225 °C. The experimental results also validated the functionality of the HV Class-D-type driver for voltages up to 60 V.

This paper presents a hardware solution to the design of general low-density parity-check (LDPC) decoders, which simplifies the delivery network required by the message passing algorithm. While many designs of LDPC decoders for specific classes of codes exist in the literature, the design of a general LDPC decoder capable of supporting random LDPC codes is still challenging. The method proposed in this paper tries to pack different check node (CN) and variable node (VN) messages in the Tanner graph representation of the LDPC code, and is therefore called message packing. This method takes advantage of the fact that for high-rate LDPC’s the CN’s degree is much larger than the VN’s, and two distinct methods for delivering the messages to the CNs and VNs are proposed. Using the proposed interconnection network (IN) results in lower complexity decoding of LDPC codes when compared to other designs. Published version

In this paper a new sense-amplifier based flip-flop is proposed for high-performance and low power application. The proposed new design employs conditional techniques to create conditional sampling windows to eliminate redundant internal transitions. The proposed single edge-triggered D flip-flop is based on charted semiconductor 0.18-mum CMOS process. The proposed design shows a great reduction in power dissipation especially at lower data activity rate, with 50% reduction at 50% data activity and 25% less power at 25% data activity. The proposed new design obtained a reduction of 21% for its data-to-output delay and an overall improvement of 30% in the power-delay-product (PDP) when compared to the recently published low-power high performance differential conditional data mapping flip-flops. It also has lesser transistor count.

In this paper, we propose a simple and novel Dual-edge-trigger flip-flop (DETFF). The design has a simple structure which consists of a XNOR pulse generator and a front end sampling circuit. All Simulations were performed at clock frequency of 800 MHz based on Chartered Semiconductor Manufacturing 0.18-mum CMOS technology. Comparison with some of the latest DETFFs shows that the proposed design can achieve the lowest power consumption and Power-delay-product (PDP). In addition, the proposed design has the least number of transistor and is of the least overall silicon area required.

This paper reports several new models of the nanocrystal flash memory cell, for use in transient simulation in Cadence environment. The models designed are then engaged in the transient simulation of the overall architecture of the nanocrystal flash memory, which includes programming, erasing, and the reading operation of the cell.

Bayesian network (K.B. Korb and E. Nicholson, 2004) has received considerable attention in a great variety of research areas such as for artificial intelligence, bioinformatics, medicine, engineering, image processing, and various kinds of decision support systems. But up till now, most of the investigation on Bayesian network has been on its theory, algorithms and software implementations. This paper presents the Bayesian network from a totally new perspective-hardware circuit implementation. By using the new-born technology of probabilistic CMOS (PCMOS) (K.V. Palem, 2005), (S. Cheemalavagu et al.), (S. Cheemalavagu et al., 2004), (P. Korkmaz, 2006) and taking advantage of the statistical properties of simple logic gates, the Bayesian network can be constructed using hardware circuits. Such hardware implementation revealed the advantages in aspects of power consumption, delay time and quality of randomness.

In this project, we have carried out researches related to displays: low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) and bistable liquid crystal displays (LCD). RG 16/99

In this thesis, solid solution of mixed zirconium oxide and iron oxide for the application of gas sensing are studied. In this study on semiconductor oxide based gas sensors, the high-energy ball milling technique was used to prepare the nano-sized powders. RG 65/98

First part aimed at producing varied planarization schemes that are suitable for both the Shallow Trench Isolated test structures and the Static Random Access Memory structures. Second part, the direct-wafer bonding process was employed to arrive at the Silicon-On-Insulator substrates. RG 46/96

This paper presents a broadband inductor-less variable gain amplifier (VGA) with a linear-in-dB gain control characteristic and DC-offset cancellation. The proposed VGA is composed of a variable gain block, an exponential voltage generator, a DC-offset canceller with common-mode voltage correction, and a gain peaking block. To achieve the broad band and reduce the chip area, the gain peaking block employs an inductor-less gain peaking scheme to compensate the high frequency gain drop of the variable gain block and the DC-offset canceller. The VGA fabricated in 0.13 μm SiGe BiCMOS technology achieves a 3-dB bandwidth of 7.5 GHz and a variable gain range from −10 to 30 dB. Due to the inductor-less design, the die area is only 0.53 × 0.27 mm^2 which is the smallest among other similar reported works. At 10-Gb/s, the VGA consumes 50 mW power from a single 1.2 V supply and exhibits an output data jitter of less than 30 pspp.

Wireless communications is ubiquitous nowadays. Mobile devices such as smart phones, iPADs and laptops are commonly used for the exchange of information between users and/or machines. With the increasing demand for high speed wireless communication system to support consumers’ needs for real time streaming of high definition (HD) video and fast file transfers, high data rate is required in the radio systems. In addition, the radio system must be compact, low cost and low power for especially for commercial wireless application. Six-port receivers have been attracting attention at the mm-wave frequencies. They offered many advantages as compared to the conventional receiver architecture at the mm-wave frequencies in terms of bandwidth, size and power consumption. Six-port receiver consists of three building blocks namely six-port correlator, power detection and baseband recovery. The six-port correlator is the fundamental building block of a six-port receiver. However, it suffers from non-ideal effects such as amplitude imbalance and phase imbalance contribute by its building blocks. In this thesis, analysis had been done on non-ideal effects such as the amplitude and phase imbalance of the two of the literature six-port correlators. Through the analysis, two novel six-port correlators were designed and sent for fabrication. Eventually, the two proposed six-port correlators were simulated together with the power detectors and amplifiers to demonstrate its intended operation as six-pot receivers. Doctor of Philosophy

With the advent of hand held computing devices that require functionality rivaling the desktop, low-power and high-performance systems have become very important. The transistor network contributes mostly to the overall power dissipation and is becoming a major obstacle in implementing those systems. Hence, the need for high performance basic sequential element with low-power dissipation is steadily growing. The aim of this project is to develop a new type of multiplier to fulfill this need. In this report, for the first time, a multiplier design concept that engages accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, we can break-through the bottleneck of conventional digital IC design techniques to improve on the performances of power consumption and speed. The two dimensional trade-off between power and speed becomes three-dimensional, i.e. power-speed-accuracy. To realize the design concept, digital multiplier circuits were studied and a novel mechanism is proposed in this work. The new type of multiplier adopting the proposed mechanism is named Error-Tolerant Multiplier (also called ETM). As illustration, the designs of 8-bit and 12-bit Error-Tolerant Multiplier, taken as examples, are described to elaborate on the design process and detailed circuit implementation of an ETM. MASTER OF ENGINEERING (EEE)

114 p. Switched capacitor technique [1] is a well-developed technique for integrated filter design. It plays a critical role in integrated filters and mixed-signal circuit design. Well known of its advantages such as good accuracy and less external components required over its continuous-time counterpart, it is becoming increasingly popular in commercial application. With the advance in CMOS process, the possibility to achieve high accuracy capacitors makes switched capacitor filter's performance more reliable. MASTER OF ENGINEERING (EEE)

Low Density Parity-Check (LDPC) codes have received lots of attention during the past decade due to their near Shannon-limit performance and decoding at very high rates. However, several issues have been raised in the research work with an aim to achieve the practical implementation of the LDPC codes. The first major issue is the performance evaluation of the LDPC codes and their decoding algorithms in the very low bit error rate (BER) regions. Unfortunately, there have so far been no analytical tools for the performance investigation of LDPC codes and one has to study such codes through simulations. The main problem with the simulations is their prohibitive execution time, especially for applications that require extremely low BERs such as data storage devices. Another concern is the efficiency of the decoding algorithm known as the Sum-Product algorithm. The Sum-Product algorithm is not optimized for short length codes and codes with cycles in their bipartite graph representation. On the other hand, the iterative decoding algorithm is computationally intensive, which imposes a high cost on area and power consumption of the decoder. The third issue is the design of the LDPC decoders to support different code lengths, rates and modes of operation. MASTER OF ENGINEERING (EEE)

High temperature electronics find many applications such as down-hole drilling, aerospace, automotive and nuclear. Elevated temperatures are required for these applications to operate reliably. Electronics for drilling application explore oil wells by sensing, logging and processing data like temperature, inclination, heading and pressure of the strata. Data acquisition system’s biggest challenge for down-hole-drilling application is the very high operating temperature, which may be up to 200 °C under more than 2 km of the earth’s surface. At high temperature, bulk-CMOS transistors exhibit many drawbacks: increase in junction leakage, shift of threshold voltages, and reduction of mobility. Among these drawbacks, the most serious problem is the excess junction leakage current at high temperature. Circuit performance is reduced due to the loss of charges at dynamic node or the loss of bias current or more seriously, the latch-up. A proper technology choice is a first consideration for successful operation of integrated circuits in such high temperature regime. By getting rid of the reverse-biased diodes between substrate/well and the source/drain region, Silicon-on-insulator (SOI) technology significantly reduces the leakage current while keeping most of the desirable properties of bulk CMOS technology. Wireless telemetry system for Measurement While Drilling operations, which is also known as Logging While Drilling, is an effective way to improve drilling operations’ efficiency. The front end amplifier is the most critical component of the receiver in a wireless telemetry system. The noise performance of the front-end amplifier determines the detection accuracy of the overall system. Front-end amplifiers used in down-hole-drilling wireless telemetry system at low frequencies is a main challenge due to the flicker noise of the MOS transistors. Power efficient high temperature capable preamplifiers with low input noise are required. In this thesis, two high temperature low-noise 1-µm partially depleted (PD) SOI CMOS preamplifiers for wireless telemetry system are presented. These designs are targeted for operation at up to 200°C. To achieve low flicker noise, PMOS devices, operating in moderate inversion, are used for the differential input of the preamplifier. MOS devices in the deep triode region are used for resistive source degeneration to reduce flicker noise and the effective transconductance of NMOS devices. Simulation shows that the input-referred noise of the preamplifier is 83 nV/sqrt(Hz) at 800 Hz. The chopper technique is chosen mainly for its very low noise performance at low frequency. For the three opamp chopper amplifier, simulation shows that the output-referred noise is 25.6 nV/sqrt(Hz) at 800 Hz. The purpose of these designs is to investigate low noise performance of the front end amplifiers under high-temperature condition. Both the circuits are fabricated using XFAB SOI 1-µm process. Experiments prove that the preamplifier can work properly at the temperature 180 °C with a gain of 17.65 dB at 20 kHz and the chopper amplifier can work properly at 225°C with a gain of 19.65 dB at 20 kHz. MASTER OF ENGINEERING (EEE)

In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. To overcome all the possible errors is a very expensive task. It not only consumes a lot of power but also degrades the speed performance. With the concept of “error-tolerant” (ET), which allows the existence of certain amount of errors, improvements in power consumption and/or other performance metrics can be achieved. In this design, the concept of error-tolerant has been extended to the field of circuit design. When “imperfect” algorithms and circuit structures are employed, a substantial yield for an error-tolerant digital circuit, in terms of power consumption, speed performance, and transistor count, can be realized. An adder is the basic digital circuit component, which is widely used in many areas. Adopting the ideas and techniques in Error-Tolerant technology in the design of digital adders, a innovative type of adder—Probabilistic Adder for Error-Tolerant Application (ETA) has been designed. In conventional design, obtaining high speed usually means more power will be consumed and low power will normally degrade the speed of a circuit. To breakthrough this bottleneck in conventional technologies for designing a truly low-power and high-speed digital circuit, a new metric besides power and speed should be brought into the design process. In the proposed designs, accuracy plays the role of such a new metric. By sacrificing some degree of accuracy, great improvements in both power consumption and speed performance can be achieved. Several different implementations of the enhanced ETA have been proposed in the report, namely the ETA Type II (ETAII), ETA Type III (ETAIII) and ETA Type IV (ETAIV). The ETAII is based on the idea that in most cases the carry signal for a bit position is determined by several neighboring bits instead of all the bits on its right. Hence, the critical path of the whole circuit can be greatly curtailed by dividing the whole adder into a number of blocks and conducting the addition operations in each block concurrently. MASTER OF ENGINEERING (EEE)

This thesis proposes a gm-enhanced differential Colpitts voltage-control oscillator (VCO) that initiates oscillation with a lower biasing current and exhibits a better phase noise performance. The proposed gm-enhanced topology can improve performance of VCO, whereby the oscillator constructed based on the suggested topology demonstrated operation from 1.53 GHz to 2.1 GHz. The tank inductors engaged in the oscillator are each designed with a quality factor of 9. To evaluate the design, a conventional cross-coupled differential LC VCO, a conventional differential Colpitts VCO and the proposed VCO are simulated using 1.5 V supply voltage, under the 0.13 μm standard CMOS process. Biased with a current of 3 mA, the simulation results show that the proposed VCO's phase noise performance is of -128.9 dBc/Hz at 1 MHz offset, which is 3.6 dBc/Hz better than that of the cross-coupled differential LC VCO and 2 dBc/Hz better than that of the conventional differential Colpitts VCO. In the post-layout simulations of the proposed VCO and conventional cross-coupled differential LC VCO, the former has a 2.1 dBc/Hz phase noise better than that of the conventional one. Based on the developed designed gm-enhanced topology, a gm-enhanced differential Colpiits Quadrature VCO (QVCO) is designed. Operating at 1.8 GHz, the proposed QVCO shows a phase noise of -132.4 dBc/Hz at 1-MHz offset, when biased with 4-mA current and 1.5 V supply voltage. Compared with the conventional Colpitts QVCO, the proposed gm-enhanced differential Colpiits QVCO demonstrates better phase noise of 4 dB under the same operating condition. MASTER OF ENGINEERING (EEE)

In recent years, there is a great deal of interest in the three-dimensional integrated circuit (3D IC). By stacking multiple active device layers with vertical interconnect, 3D IC technology provides great opportunities for designers to meet power and performance requirements. In this research, the innovative 3D IC technology is employed as a basic tool. In addition to the conventional horizontal dimension, active devices are stacked in the vertical dimension in 3D IC technology. The additional degree of connectivity in the vertical dimension enables circuit designers to replace long horizontal wires with short vertical interconnects, so that delay, power consumption, and area can be reduced. The design problem of miniaturized wireless sensor node has been explored and a digital core design in wireless sensor node is proposed in this work. The design aims to provide an efficient solution for recording users’ bio-vital data, as well as to transmit, extract and deposit the information on the platform. This capability serves to monitor the progression of chronic diseases. The 3D architecture for a wireless sensor node will be discussed in-depth and the impact of 3D-integration technology on conventional digital circuit design will be demonstrated in this project too. Through silicon via (TSV) based 3D integration technology is employed as the vertical interconnect methodology. The proposed design methodologies described in this thesis are intended to strengthen the 3D design capabilities, making this fascinating technology a promising solution for future integrated systems. Functional tests were conducted to validate the overall systems usability and modularity and the measured results proved that reliable data transfer and continuous bio-vital data monitoring can be consistently achieved. The measured results validated the approaches chosen, and verified that the system is useful in patient monitoring application. The next phase of the work will be to implement the proposed digital core design in 3D wireless sensor node in field programmable gate array (FPGA). MASTER OF ENGINEERING (EEE)

In this dissertation, the fault diagnosis approaches based on machine learning algorithms are discussed. For industrial processes, faults may be caused by a network attack. In this project, the data packets on the internet will be captured and processed to extract some useful information. Back propagation network and support vector machine are the most popular machine learning algorithms, which have many advantages such as quick and efficient. In the project, lots of historical network data will be trained by the above two algorithms and tested to obtain an optimal fault diagnosis approach. Master of Science (Electronics)

The widely used LED lighting driver is series resonant (SR) converter or parallel resonant (PR) converter, which has a simple and understandable topology. The efficiency of conventional LED lighting in the market is around 90% to 92%. In this dissertation, an improved design with high efficiency reaching up to 97% to 98% based on traditional topology is proposed. Gallium Nitride (GaN) devices instead of standard MOSFETs are used in this novel design, in order to achieve a higher frequency operation up to 1 MHz with less performance loss for the switched mode power supply design. Additionally, magnetic size is reduced significantly by operating the converter at higher frequencies, which is better for applications in very limited space with small form factors. However, hard switching is no longer able to achieve satisfied performance under high frequency operation, hence soft switching is applied in the circuit design instead. This thesis details the design of a digitally controlled and credit card size LED lighting driver. This LED converter is converting from 380 VDC to 300 VDC to drive the new outdoor lighting with high efficiency, designed to work for constant current output (500 mADC) for LED lighting for commercial applications using GaN devices. The LED driver will also feature DALI communication protocol for remote monitoring and control. Master of Science (Electronics)

The technology for obtaining information from big data has broad application prospects. Among them, the information contained in the text is direct and efficient, furthermore the digitizing of the text information is of great significance for improving capabilities of both the multimedia retrieval and scene understanding. Recently, the identification of document text is mature. But the recognition of text in images, especially in natural scene images, which is important and challenging, is still in the stage of research and exploration. Because when dealing with natural scene images, even if using deep neural network models, we still have problems. The reason is that the overall performance of the network depends on the interaction of multiple stages. So that we want to propose a simple, effective and fast network for text detection. This dissertation explores the transition from object recognition to text recognition and the development of natural scene text recognition. A brief review of the principles, structure and design of the deep learning method of text detection, namely the convolutional neural network method. Then we present a simple and useful network that produces fast and accurate text detection in natural scene images. The network can directly predict words or lines of text in any direction and quadrilateral shape in the image, eliminating unnecessary steps. From the experimental results, we can see the accuracy and efficiency of the algorithm, and then propose an improved method in the dissertation. Using the improved method, the calculation speed is improved, the work efficiency is improved, while the accuracy of the text detection result is maintained. By analyzing the experimental results, we confirmed that this is a useful algorithm. Finally, the conclusion and recommendations about the further research will be given. Master of Science (Electronics)

Spiking neural network (SNN), largely inspired by a biological neural network, offers many advantages over the conventional deep neural network (DNN) [1]/ convolutional neural network (CNN) [2] in energy efficiency and latency due to its event based processing, which makes it a good candidate for energy efficient voice classification. Furthermore, the learning mechanism of the SNN typically requires only local information of pre-synaptic neuron and post-synaptic neuron when a spike happens, providing a light-weighted energy-efficient and hardware-friendly solution for the applications of voice recognition and classification. This dissertation reports a digital spiking neuron based on Leaky Integrate-and-Fire (LIF) model [3]. As the basic units of neurons in SNN, several LIF models jointly construct a 3-layer neural network. Subsequently, eight Infinite Impulse Response (IIR) digital filters ranging from 0 Hz to 400 Hz are designed to analyze human voice in both time and frequency domains, which extracts the feature of male and female voices. Two thousands male and female voice clips are used as training sets and five hundred voices are used as test sets in the neural network. The functionality and performance of the proposed digital spiking neuron can be verified by test sets to recognize male and female voice. The obtained results and simulations in MATLAB demonstrate the superiority of the proposed SNN and determine the potential of such systems in voice classification. Master of Science (Electronics)

The focus of this dissertation is to investigate on know how to trim and calibrate Global Navigation Satellite Systems (GNSS) receiver chain of a cellular phone for efficient characterisation. Trimming and calibration is performed on Phase-Locked Loop (PLL), Analog to Digital converter (ADC), Local Oscillator (LO) and Low-Dropout (LDO) Voltage Regulator blocks in the receiver chain. Additionally, resistors and capacitors are also trimmed to improve the performance of the Trans Impedance Amplifier (TIA). A detailed study is carried out in literature survey to explore the existing methods to trim and calibrate the above-mentioned blocks and components in the Radio Frequency (RF) receiver chain. Phase-Locked Loop (PLL) and Analog to Digital Converter (ADC) calibration is done in an automatic manner by using digital trim techniques and auto calibration units upon board power on. Resistor, Local Oscillator (LO) and Low-Dropout (LDO) Voltage Regulator calibration are done manually by enabling and writing the corresponding trim registers installed in the chip after board power on. With technology scaling, design of analog devices has become more complex as it depends on balancing many parameters. Post-production performance calibration is used to balance the parameters. Tuning knobs are added across various blocks in an analog circuit at the design stage to mitigate variations after production. Tests are carried out in Automatic Test Equipment to quantify variations in the performance specifications and these variations are fused in to a non-volatile memory embedded in the chip. The applications of these variations during bench validation is called trimming and calibration. The bench validation process starts with trimming and calibration before actual validation is carried out to achieve improved accuracy. Once the chips arrive from production, they are powered on to read the trim codes from the memory. This procedure is carried out across Typical, Fast and Slow corners. Once the trim codes are read the best code is selected for optimised performance for every design block. In this dissertation I will be discussing the trimming and calibration procedure for Resistor, Capacitor, Phase-Locked loop (PLL), Local Oscillator (LO), Low-Dropout (LDO) and Voltage Regulators. Master of Science (Integrated Circuit Design)

With economic globalization and the rapid development of the Internet, the connections between different countries and languages have become closer and closer, which sharply increase people's demand for cross-language communication. Traditional human translation which has many weaknesses cannot meet the needs of a wide range of translations. Artificial intelligence technology has been applied, Machine translation technology is an effective way to realize automatic translation and solve the increasingly common cross-language communication. The statistic machine translation can previously satisfy the minimum requirement of translation, but it requires many improvements. The work of this dissertation is to explore possible application of deep neural network and combine the current popular Recurrent Neural Network (RNN) system to achieve high performance machine translation. After comparing the advantages and disadvantages of different improvement models for RNN, Long Short-Term Memory (LSTM) [27] which is a more complete experimental algorithm model for the encoding and decoding process is engaged in this dissertation. Two kinds of Neural Machine Translation (NMT) models are available, the classical NMT model with greedy decoding, and the NMT model with attention mechanism [32], both were reviewed and explored in this study. Following which the BLEU i evaluation method is used to index the performance of two models, and the results obtained verify that the NMT model with attention mechanism has 1.9 BLEU value higher than the greedy decoding NMT model in training, and 2.3 BLEU value higher than the greedy decoding NMT model in testing, which directly proves the NMT model of the attention mechanism is improved for the performance of neural machine translation. The translation results have also been compared in three different size of sentences, from which conclusions can be got that normal NMT does well in short sentences only, but lose its power in middle and long sentences, while NMT model with attention mechanism act nicely in all three types of sentences. Whereas, some problems occur like excessive translation, which needs future exploration. Master of Science (Electronics)

With the popularity of the Internet, more and more businesses and transactions rely on the network to complete, and at the same time, anomaly attacks against various network applications are becoming more and more frequent. How to detect and identify various network anomalies has become an unavoidable technical issue. The network attack methods emerge in an endless stream, and the attack methods are constantly updated, making the traditional security mechanisms such as firewalls difficult to detect for many attacks. As an effective defense technology, intrusion detection technology makes up for the shortcomings of traditional security technology and has been concerned by researchers at home and abroad. With the continuous expansion of network scale, the continuous growth of network traffic and the continuous development of hacker technologies, higher requirements are placed on the performance of network anomaly detection. This thesis designs an anomaly attack detection based on self-organizing mapping algorithm to improve the accuracy of anomaly detection technology. Through the unsupervised machine learning method, the daily data of the transportation system is clustered and a training model is established. Finally, abnormal attack detection is performed according to the clustering model. Master of Science (Electronics)

The brain wave signal is derived from the synaptic potential caused by the synchronization of many neurons, reflecting the electrophysiological activity of brain neurons, which carries a large amount of biological information. The information contained in EEG has important research and application value, especially it can provide an important basis for clinical diagnosis and treatment. However, it is not easy to detect EEG signal. The EEG signal is very weak, generally only about 50 μV, and the amplitude range is 5 μV~100 µV. EEG signal scalp and skull usually have a resistance of several thousand ohms, so the front part has a high input impedance. The frequency, generally 0.1~100 Hz, of the EEG signal is low, and EEG signal acquisition in the normal environment is affected by common mode interference such as power frequency interference, since the signal-to-noise ratio is usually lower than -10 dB. Therefore, when we design the acquisition circuit, higher amplification gain, greater input impedance and low-pass filter are the required technical indexes. In general, EEG signal is enlarged by about 20,000 times, the input impedance is greater than 10 MΩ to improve the EEG signal acquisition ability. Besides, the amplifier in circuit is required to have a high common mode rejection ratio (CMRR), which is generally greater than 120 dB, because power frequency interference mainly exists in the form of common mode, and the amplitude is on the order of mV. To satisfy the requirements of EEG signal acquisition circuit, ICL7650 chip is employed in the design, since it has some good characteristics such as high gain, high CMRR, low offset and so on. After accessing information online, a suitable structure of the acquisition circuit based on ICL7650 is determined. Then to verify the function of each module in the circuit. We used Multisim to perform the simulation of circuit. According to the resulted waveforms, the circuit can execute the amplifying and filtering function normally. Master of Science (Electronics)

Neural network computing has attracted a lot of attention as it borrows the concept of human brain to achieve artificial intelligence (AI). AI has been used in many applications such as energy estimation and battery management in smart grid, and image/audio recognition in intelligent robots. The limitation of software-based neural network computing include low speed and high power consumption, making it difficult to be used in real-time and portable applications especially when the required accuracy is high. To address this issue, hardware based neural network computation have been investigated. However, the challenge is to map different neural network topologies to a hardware accelerator platform with fixed processing engine array in an efficient way so that the latency and energy consumption is minimized. Convolutional neural network (CNN) is highly complex. In this dissertation, optimal mapping of different neural network topologies to FPGA (Field-Programmable Gate Array) will be investigated. The main work is to study the neural network topologies, the processing engine array based on FPGA and a methodology to map a specific network topology to the platform. This will include the mapping of computation, data transfer and control part. The main optimization objects include latency and energy efficiency. Some research on training will be introduced, which can achieve by using software Matlab. Training process includes supervised and unsupervised learning. Another focus is the implementation of process engine architecture. Some architectures have been proposed and one preferred architecture was implemented on the hardware platform. In this project, one layer structure is achieved and simulation results by Vivado will be analysed. Master of Science (Electronics)

Diabetes diagnosis and condition surveillance are two main challenges in treatment of this disease. One of the methods is to use plantar pressure which will show different pattern according to different disease conditions of diabetes. One problem of this approach is identifying the activity of the patients since different activity may naturally result in various plantar pressures. This dissertation aims at solving this problem by using accelerometer data to recognize human body activities which include walking, jogging, jumping, going upstairs and going downstairs. Beginning with the preliminary data collection work, several approaches to process raw signals and classify different activities from the acceleration data recorded by accelerometers are proposed and tested by this dissertation, where PCA feature extraction method, time and frequency analysis, SVM classifier and RBF Neural Network are involved. Besides, a window segmentation method and the classification strategy based on small windows are introduced. By combining and doing experiments on these methods, PCA feature extraction method and SVM classifier are proven to have the best performances, which can achieve a classification accuracy up to 92%. While the time and frequency domain features, which has been applied by most of the existing works, show poor performances under the experiment environment in this dissertation. Master of Science (Computer Control and Automation)

With the rising prevalence of industrial Internet of Things (IoT) devices, it has become more important to ensure that IoT devices are secure. A method that attackers use to gain access to the IoT devices is to spoof themselves as the IoT server. Traditional authentication methods need a lot of memory resources, which is unable to meet the needs of lightweight IoT devices. The idea of the new authentication protocol is to use the historical data exchanged between an IoT device (verifier) and a server (prover) as a second authentication factor, in addition to the conventional factor of a shared secret key. The new authentication method needs more memory resources of server instead of IoT devices, which is what people want. However, the historical data authentication factor is considered a big dataset and the retrieve of selected pieces of data from a large data pool usually encounters long latency if the algorithm and implementation are not well optimized. To reduce latency, three methods are proposed in this dissertation. After presenting the new authentication method using historical data and optimizing it, a real system is implemented. Because the IoT devices are normally unable to verify the legality of the server, BeagleBone Black (BBB) (a kind of single board computer) is used to verify. Thus, the communication between the IoT device and BBB and between BBB and server are key problems. A structure named “bridge” is built and in order to insert verifier process, ip_queue in Linux is adopted. Thus, an optimized authentication process using historical data can be run in this system. Master of Science (Electronics)

Human behavior monitoring technology is widely used in medical rehabilitation, health care and human-computer interaction. Human activity recognition based on accelereometer is a new research field of human behavior monitoring. Compared to the human activity recognition method based on vision, it offers numerous advantages such as anti-interference ability, portability, data acquisition free, etc. However, the existing wearable human behavior monitoring system requires a large number of nodes, large power consumption, and poor endurance. Therefore, it is of great significance to design a new wearable human body activity monitoring device that is practical and convenient to use. This dissertation describes the human activity recognition and analysis based on the FPGA (Field Programmable Gate Array) Spartan-6 LX9 Microboard and ADXL345 three-axis accelerometer. In order to reduce the power consumption, MicroBlaze processor embedded in the FPGA Microboard is used to control the three-axis accelerometer. The ability to distinguish slow walking, normal walking and fast walking is dealt with using the proposed walking pattern recognition algorithm based on wavelet energy and IQR (Inter-Quartile Range). Analysis showed that the proposed extraction method can achieve an average recognition rate of 100%, which truly validate the proposed feature extraction method. A recognition algorithm based on standard deviation, skewness, kurtosis and correlation coefficients is also proposed to identity 5 walk pattems, i.e., standing, walking, running, going upstairs and going downstairs. By comparing the K-NN (K-Nearest-Neighbor) and SVM (Support Vector Machines) classifier models, it was found that when using SVM for classification, the behavior recognition rate of standing, walking, running can reached 100%. In other words, human behavior recognition based on three-axis accelerometer is an important research field of activity recognition. It has wide application prospect for wearable human body detection device. Master of Science (Electronics)

With the rapid development of Artificial Intelligence, the Autonomous Vehicle Technology has gained a huge amount of attention. However. it is extremely time-consuming and of high-cost to design, develop, manufacture and test the actual autonomous vehicle in real world. A proper simulation for autonomous vehicle based on physical simulation engine, such as gazebo, which allows match the actual situation and checking of performance before the actual production and manufacturing of the real autonomous vehicle. In this dissertation, the main target was to build a 3D model in a virtual environment based on Gazebo for the target autonomous bus, where several simulated sensors such as Lidar, sonar, camera, Global Position System and Inertial Measurement Unit for sensing object's acceleration velocity will be added to the intended 3D bus model to capture real-time that are generated by simulated sensors. Meanwhile, the Robot Operating System (ROS) will be applied to add the ROS nodes to the 3D bus model for the further data visualization based on 3D visualizer, such as Rviz, and communication between these corresponding nodes of sensors. Lastly. Based on the existing drawbacks of communication mechanism in ROS, a corresponding method has been proposed to improve this defect. Besides, the general simulation performance for this 3D autonomous bus model based on Gazebo and ROS will be analyzed. Master of Science (Electronics)

In recent years, CMOS-based conventional memory technologies including SRAM, DRAM, and Flash memories have become system performance bottleneck due to the speed gap between memory and logic, where they consume a large portion of power within systems, and not only that, they will soon face technology and economic issues as CMOS scaling approaches the fundamental limit. Emerging Non-Volatile Memory (NVM) technologies such as Magnetic RAM (MRAM) and Resistive RAM (RRAM) are recognized as promising candidatures for next-generation memory systems owing to several appealing properties: non-volatile, high density and scalability, fast speed, universal adaptability and multiple-bit capacity. In addition to be memory storage, NVM also offers many unique applications based on its physical properties. In this dissertation, the author has reviewed two typical NVM technologies, including MRAM and RRAM, and their related applications. The MRAM is thereby selected as a case study to explore security application, i.e., Physical Unclonable Function (PUF) circuit design. A modified MRAM model is established by Verilog-A and the MRAM model, which includes statistical distribution of physical parameters for Monte Carlo simulation that models the process variation of Magnetic Tunnel Junction (MTJ) in MRAM. By utilizing the mismatch variation of MTJ device for Internet of Things (IoT) hardware security application, a MRAM based PUF has been designed. Statistical data are generated using the Cadence Measurement Description Language (MDL) with Spectre simulator to perform mixedlanguage Monte Carlo simulation. A dual-mode MRAM architecture, including MRAM arrays and sense amplifier (SA), has also been studied and explored to implement functions of both memory and PUF. The simulation calculated are based on 65 nm CMOS technology and 45 nm radius MTJ. Master of Science (Electronics)

The Internet of things (IoT) is the networked interconnection of every object to provide intelligent service and improve economy benefit. The potential of IoT and its ubiquitous computation reality are staggering, but limited by many technical challenges. One challenge is to have a real-time response to the dynamic ambient change. Machine learning accelerator on IoT edge devices is one potential solution since a centralized system suffers long latency of processing in the back end. However, IoT edge devices are resource-constrained and machine learning algorithms are computational intensive. Therefore, optimized machine learning algorithms, such as compact machine learning for less memory usage on IoT devices, is greatly needed. In this thesis, we explore the development of fast and compact machine learning accelerators by developing least-squares solver, tensor-solver and distributed-solver. Moreover, applications such as energy management system using such machine learning solver on IoT devices are also investigated. From the fast machine learning perspective, the target is to perform fast learning on the neural network. This thesis proposes a least-squares-solver for single hidden layer neural network. Furthermore, this thesis explores the CMOS FPGA based hardware accelerator and RRAM based hardware accelerator. From the compact machine learning perspective, this thesis proposes a tensor-solver for deep neural network compression with consideration of the accuracy. A layer-wise training of tensorized neural network (TNN) has been proposed to formulate multilayer neural network such that the weight matrix can be significantly compressed during training. From the large scaled IoT networks perspective, this thesis proposes a distributed-solver on IoT devices. Furthermore, this thesis proposes a distributed neural network and sequential learning on the smart gateways for indoor positioning, energy management and IoT network security in IoT systems. Doctor of Philosophy (EEE)

With the growing focuses on fitness and Neuromuscular diseases, a type of biomedical devices which can monitor skeletal muscle contraction have become more and more popular. The muscle action potential which can be generated across Sarcolemma is a crucial parameter to help doctors to monitor the muscle contraction and classify Neuromuscular diseases for their patients. The muscle action potential can also help fitness coach to know whether a trainer is using a right muscle. A wireless skeletal muscle contraction monitoring device includes: ① a front-stage acquiring circuit, which can extract the electromyography(EMG) signal from muscle through surface electrodes, ②a wireless communication circuit, which is a Bluetooth module names HC05, ③a Analog to Digital Converter (ADC) circuit which is implemented by msp430 micro controller from Texas Instrument, ④ a signal receiving and processing software – LabVIEW software in Personal Computer which can receive sample data of sEMG signal from the device via Bluetooth communication. This dissertation focused on the wireless communication circuit design, ADC circuit design and LabVIEW software design. In order to detect the muscle contraction, two sensor channels were used by using two electrodes. The data sampled by the front-stage acquiring circuit is converted to a serial digital signal. So a msp430 micro controller which has an ADC function is used. For wireless communication between laptop and the monitoring device, a Bluetooth module is combined with the device. In the meantime, simulation and testing on the front-stage acquiring circuit were carried out to verify the function. Lastly, in this stage of the project, a LabVIEW software is designed to receive the signal data from the monitoring device and to derive the electromyogram waveform for future analysis. The performance of the system is investigated by experiments and tests. Different amplitudes of sEMG waveform represent different muscle movement. Master of Science (Electronics)

Human medical data collection system, especially patient monitoring system is always a challenge for designers. The system should be able to extract weak electric signal from strong common-mode voltage and noise. Besides, conventional electroencephalogram (EEG) monitoring systems are usually bulky, expensive and power hungry, which is not convenient for family use. Therefore, in this project, a portable wireless monitoring device with high common-mode rejection ratio (CMRR) analog-end and high digital resolution is designed. The device mainly contains two parts: the front-end (i.e. analog part) and the back-end (i.e. digital part). The analog part is made up of high CMRR amplifiers, precision operational amplifier and low-pass filter; the digital part mainly assembles the Analog-to-Digital Converter (ADC) and Bluetooth transmission module. The analog electric signal from electrodes can be amplified about 600 times by amplifiers, then the bandwidth is filtered to range 20 – 500 Hz. After being biased, the signal is sampled and converted by SAR ADC and then sent to PC or mobile equipment through Bluetooth module. Finally, the signal received will be observed and analyzed on LabVIEW. The performance of the entire system has been tested by amounts of simulations and analyses from design-stage to testing-stage. The experimental results show that the EEG signal can be detected and processed accurately by this wireless EEG monitoring system. Besides, the device can also be used to detect electrocardiogram (ECG) and electromyogram (EMG) signal. Master of Science (Electronics)

Wireless power transfer (WPT) is a potential technology that enables transmission of electrical power without the necessity of electrical contact. WPT can be employed in a wide variety of applications and this can be achieved due to WPT’s inherent advantages over its wired counterpart. These advantages enable WPT to eliminate numerous drawbacks faced by its wired counterpart. However, even with much research interest in this technology, WPT still need to overcome numerous technical challenges before it can truly be ubiquitous in the modern connected world. This thesis has proposed several approaches to improve WPT’s performance in terms of efficiency, transferred power, etcetera. In addition, a novel control scheme for dynamic WPT (D-WPT) systems without needing external sensors, and this helps solve some complexity and implementation issues of a D-WPT system. WPT systems use inductive coils and its electromagnetic coupling to transfer power wirelessly without electrical contact. These loosely coupled inductive coils are powered by high frequency power sources and cause large leakage inductances and input impedances. By employing compensating capacitors and electromagnetic resonance operation, the input impedance and VA (volt-ampere) rating of the WPT system can be significantly reduced, leading to an increase in the performance in terms of efficiency and power transfer, as well as transfer gap distance. However, there are many different types of compensation circuits available for WPT systems and these compensation circuits perform differently under varied conditions. The thesis dwelled into the circuit analyses on the various compensation circuits and derives the efficiency optimal operating frequencies these WPT systems. Using the optimized operating frequency, the efficiency analysis of these compensation circuits are detailed. Resonant frequency responses of the compensation circuits are used to further differentiate. With these analyses, the efficiency orientated design flow chart for selecting the optimized compensation circuit is derived with consideration for efficiency, load resistances, transferred power, transconductance and voltage gain. Experimental results also verified the usefulness of the flow chart and its respective analyses, which showed efficiency discrepancy of 28% (highest at 500 Ω) equivalent output resistance when comparing between compensation circuits. The LCC compensation circuit is also analyzed and its frequency bifurcation effect is investigated to be significantly mitigated. The LCC compensation circuit also shows significantly higher transferred power and lower harmonic distortion. The concept of Dynamic WPT (D-WPT) is to allow the receiver (Rx) to move freely while receiving power from the D-WPT system wirelessly. The thesis proposes a novel control scheme for the purpose of individual magnetic coupler control using the sensed transient response of the magnetic coupler’s input current. This would improve the D-WPT system’s efficiency, while circumventing the necessity for external positional sensors or auxiliary circuitry. The proposed control algorithm yielded a low standby power to operating power percentage of 7.2% as compared to 44.2% found in existing literatures. Thus, the proposed control algorithm for D-WPT system could be a promising approach to reduce D-WPT system complexity, improve power consumption and EMI/EMC performances during standby mode, as well as power transfer efficiency levels. Doctor of Philosophy (IGS)

Distributed Denial of Service (DDoS) attack has become one of the major threat to current Internet. The attacker firstly gains the control of a large number of hosts. Then by controlling these hosts to send illegal packets to the victim simultaneously, the attacker can easily exhaust the bandwidth or computing resource of the victim. DDoS attack mitigating approaches that apply pre-established defending strategy, functionality or capacity, and guard at fixed locations are costly and not effective. Software Defined Network (SDN) is a new network architecture in which the data plane and the control plane are decoupled. In SDN, the data forwarding function is achieved by using general devices while the control function is implemented by software. Network Function Virtualization (NFV) supports the flexibility in on-demand function instantiation and allocation, and recently finds its applications in handling DDoS attacks. In this dissertation, NFV/SDN is applied into DDoS mitigation. In the framework, network traffic is monitored and analyzed utilizing the SDN features of central control and global network view, and the detection of anomaly traffic will trigger the actions of SDN controller. In this dissertaion we build up an SND environment and demonstrate a DDoS attack on a network topology. By doing simulation experiment, see how we can mitigate it using SDN in real-time. It is shown that the SDN controller can identify the DDoS attackers and disconnect them from the network to prevent any further damages to the network. Master of Science (Electronics)

With the rapid advancement of science and technology, IoT networks have gradually grown to larger scales. In the recent years, overall structure of IoT network has become more complex, and the abnormal behavior of networks has also become increasingly complicated. In order to better improve the effectiveness of the IoT network to prevent anomalies, it is necessary to accurately study and analyse the abnormal behavior of network when anomalous behavior occurs, as well to solve and prevent the anomalies that exist in the network, thereby reducing their impact. This dissertation focused on the detection of abnormality with Wireshark and packet analysis system. An alert system also be developed to make an alert when abnormality happens. In order to be more suitable for IoT network, some IoT data is collected and analysed. From the data obtained, the network features can be used to detect the abnormality. Wireshark which is a freeware is then used to evaluate some conclusions about network packets. To improve efficiency and to reduce time delay, the packet analysis system is introduced to receive the network flow and to analyse data in real time. This will do away with human intervention to allow system automation. After detecting the abnormality of the IoT network, an alert system needs to inform the person in charge to resolve the problem. The system can play the alert music, pop up an alert window and print the alert information on the screen. With the conclusion of data analysis, the trust list can be set up to ease further development. With the two detection methods (the Wireshark detection and the packet analysis system) and the alert system, the IoT network abnormality will be detected easily and resolved timely. Master of Science (Electronics)