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We present modeling and analysis of carrier dynamics in a single-photon avalanche diode (SPAD) operated with a capacitive quenching (CQ) method. The CQ method is regarded as a conventional resistive quenching (RQ) with its quenching resistance infinite or an open circuit. The SPAD is modelled as a lumped circuit consisting of a voltage dependent charge generator representing an avalanching depletion region and a capacitance of the depletion region and parasitic components. The carrier dynamics inside the device is described by time-dependent bipolar continuity equations (BCE) derived from the carrier continuity equations. We solve the BCE numerically with a 0.1 ps time resolution and investigate numbers of carriers in each circuit element as functions of time and of excess bias voltage (|𝑉ex|). We find two important characteristics of the CQ method; (1) a single-photon triggered Geiger-mode pulse is guaranteed to be quenched in a stable state (2) a voltage drop of the internal bias of SPAD due to the charges stored on the capacitance is proportional to |𝑉ex| with the proportionality factor of two. The results, in turn, enables one to design a SPAD free from after-pulse and from overflow. Such a SPAD pixel is shown to be compatible with a conventional complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a four transistors configuration pixel circuit. Finally, effectiveness of the present methodology is demonstrated by the subrange synthesis (SRS) time-of-flight (ToF) ranging experiments using a 6 μm size 400 × 400 pixels SPAD-based CIS.

Long-range (~250m) measurement systems with 3D resolution are highly anticipated for various applications such as automotive, surveillance and robotics systems. Direct time-of-flight (ToF) systems based on CMOS image sensors (CIS) with avalanche photodiodes with the Geiger-mode or single-photon avalanche diodes (SPAD) have been developed for these purposes. One difficulty is to meet practical requirements of long-range (~250m) measurement capability together with both lateral and depth resolution. Although indirect-ToF systems based on modulation and phase sensitive detection have fine depth resolution of the order of sub-cm, their full range is limited only to ~4m with standard Si-photodiodes [1] and ~20m with the gain assist of APD [2]. Direct-ToF systems based on SPAD pixels with time-to-digital converters (TDC) have long range measurement capability but have not reached megapixel resolution [3], [4]. Another direct-ToF of sub-range syntheses (SRS) system, which detects single photons returned from an object located in each sub-range by synchronous gating, was demonstrated to have a long range (250m) measurement capability with high lateral resolution of 10cm. However, it has a depth resolution limited by the width of optical pulse source [5]. In order to circumvent this issue, in this work, we develop an SRS-ToF system based on a 6µm pitch, 1200×900pixels, Geiger-mode operated vertical avalanche photodiodes (VAPD) CIS that enables one to configure depth resolution down to 10cm for short-distance (

The intensive development of Single-photon avalanche photodiode (SPAD) based CMOS image sensors (CIS) continues, with rapid progress [1–6]. Yet, due to unestablished quenching operation [5,6], realization of SPADs onto a CIS alongside conventional pixel circuitry has been a fundamental challenge.

We present an analysis of carrier dynamics of the single-photon detection process, i.e., from Geiger mode pulse generation to its quenching, in a single-photon avalanche diode (SPAD). The device is modeled by a parallel circuit of a SPAD and a capacitance representing both space charge accumulation inside the SPAD and parasitic components. The carrier dynamics inside the SPAD is described by time-dependent bipolar-coupled continuity equations (BCE). Numerical solutions of BCE show that the entire process completes within a few hundreds of picoseconds. More importantly, we find that the total amount of charges stored on the series capacitance gives rise to a voltage swing of the internal bias of SPAD twice of the excess bias voltage with respect to the breakdown voltage. This, in turn, gives a design methodology to control precisely generated charges and enables one to use SPADs as conventional photodiodes (PDs) in a four transistor pixel of a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) with short exposure time and without carrier overflow. Such operation is demonstrated by experiments with a 6 &micro, m size 400 &times, 400 pixels SPAD-based CIS designed with this methodology.

We have developed a direct time-of-flight (TOF) 250 m ranging Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) based on a 688 &times, 384 pixels array of vertical avalanche photodiodes (VAPD). Each pixel of the CIS comprises VAPD with a standard four transistor pixel circuit equipped with an analogue capacitor to accumulate or count avalanche pulses. High power near infrared (NIR) short (&lt, 50 ns) and repetitive (6 kHz) laser pulses are illuminated through a diffusing optics. By globally gating the VAPD, each pulse is counted in the in-pixel counter enabling extraction of sub-photon level signal. Depth map imaging with a 10 cm lateral resolution is realized from 1 m to 250 m range by synthesizing subranges images of photon counts. Advantages and limitation of an in-pixel circuit are described. The developed CIS is expected to supersede insufficient resolution of the conventional light detection and ranging (LiDAR) systems and the short range of indirect CIS TOF.

We have developed a direct time-of-flight (TOF) 220 m ranging CMOS image sensor (CIS) based on a 688 × 384 pixel array of vertical avalanche photodiodes. An area scene at 220 m ahead can be ranged and imaged by one high power light pulse illuminated through diffusing (without scanning) optics and sub-photon level signals are extracted by in-pixel pulse count circuits. Depth map imaging with a 10 cm lateral resolution and with a 30 cm depth precision is realized from 1 m to 220 m range. The developed direct-TOF CIS with SPSE is expected to supersede the insufficient resolution of the conventional light detection and ranging (LiDAR) systems and the short range of indirect CIS TOF.

We developed multiocular 1/3-inch 2.75-μm-pixel-size 2.1M- pixel image sensors by co-design of both on-chip beam-splitter and 100-nm-width 800-nm-depth patterned inner meta-micro-lens for single-main-lens stereo camera systems. A camera with the multiocular image sensor can capture horizontally one-dimensional light filed by both the on-chip beam-splitter horizontally dividing ray according to incident angle, and the inner meta-micro-lens collecting the divided ray into pixel with small optical loss. Cross-talks between adjacent light field images of a fabricated binocular image sensor and of a quad-ocular image sensor are as low as 6% and 7% respectively. With the selection of two images from one-dimensional light filed images, a selective baseline for stereo vision is realized to view close objects with single-main-lens. In addition, by adding multiple light field images with different ratios, baseline distance can be tuned within an aperture of a main lens. We suggest the electrically selective or tunable baseline stereo vision to reduce 3D fatigue of viewers.

We have developed a low-temperature formation technique for ferroelectrics (

We demonstrate a fast shutdown and resumption of a logic circuit applied a nonvolatile latch having SrBi 2 (Ta,Nb) 2 O 9 (SBT) capacitors without a higher drive voltage than a logic voltage of 1.8 V. By assigning an individual drive circuit of the SBT capacitors to the nonvolatile latch not sharing a drive circuit with multiple nonvolatile latches, the fast shutdown and resumption of a logic circuit were completed in 7.5 ns at a drive voltage of 1.3 V. The fast shutdown and resumption without an addition of a high drive voltage to a logic circuit meets a requirement from power-saving applications of system LSIs fabricated in CMOS technologies at 90-nm and below.

In this paper, a new approach is described to solve some problems that occur when ferroelectric random access memory (FeRAM) is applied to logic circuits, particularly RSA cryptography. Application of a programmable switch device to RSA-based cryptography processing circuits was explored. RSA-based cryptography processing circuits have been designed as code conversion circuits. The capacity of the code conversion programmable AND gate and FeRAM and the translation rate have been investigated as a function of bit length. As a result, a problem of huge capacity at the practical bit length can be predicted theoretically. To solve this problem, we propose a new scheme for circuits and a new algorithm of logic operation using the binomial theorem.

This paper has described a new concept on programmable switch device furnished with gain cell combined to FeRAM. Compared with memories but ferroelectric memories under many aspects, they have even been favorably labeled the ideal memory because of their non-volatility, ease of programming and operation by low voltage. As the programming switch, which is very attractive for logic application, SRAM, anti-fuse, flash type devices are well known. They have been required that satisfy non-volatility and low-voltage programming simultaneously. Some structures with ferroelectric material have been proposed and studied as solution of these problems. However, it seemed hard that these type devices are realized now from a viewpoint of fabrication process and low voltage operation. Therefore, we propose a new switch device furnished with gain cell combined to FeRAM. We have studied and simulated this switch device by SPICE. This basic circuit is composed of two blocks. One is switching block that includes g...

We present a CMOS image sensor that enables a compact 3-dimensional (3D) vision camera system comprising a single set of the sensor and a camera lens. In order to make binocular parallax, which is essential for 3D imaging, the input pupil of the camera lens is presumed to consist of the right-eye and the left-eye domains, where the pixels exclusively receiving light beams from the right-eye domain and those from the left-eye domain, are arranged alternately. In addition, the sensor features an on-chip lenticular lens to split the incident light from the two directions and a Digital Micro Lens [1,2] to focus the split light beams onto the dedicated pixels without significant crosstalk. The fabricated 3D image sensor enables not only successful stereovision imaging in color with sufficiently high sensitivity, but also accurate calculation of distance.

We present a day and night MOS imager based on a single plate on-chip interference color filter. The filter comprises periodic multiple layers of TiO 2 and SiO 2 , with an intermediate color selection layer (SiO 2 ) to disturb the period of the layers, analogous to a "defect" layer in the one-dimensional photonic crystal. A particular advantage of this filter is flexibility of designing a spectral profile of each color. Thus, one unit cell of the present MOS imager is designed to have three multi-spectral, i.e. R+IR, G+IR, B+IR, pixels and one IR dedicated pixel, which would never be realized by ordinary pigment materials. Daytime color image signals are obtained by subtracting the IR pixel signal, as a reference, from each signal of R+IR, G+IR and B+IR pixels. Nighttime black and white imaging is simply realized by using the IR components of all the pixels as brightness signals. This enables seamless switching between the day and night operations of a camera. Although the subtraction operation usually reduces the dynamic range (DR) and signal-to-ratio (SNR), in particular at low color temperatures, we overcome the issues by employing a new design scheme of the color filter comprising double defect layers for each visible pass band and narrow IR pass bands for common IR components. As a result, signal degradations in SNR and DR are suppressed even at low color temperatures enabling daytime imaging in a wide range of color temperatures from 2300 K to 6500 K.