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1. Compact Equivalent-Circuit Model for Snap-Back Phenomena in Ultra-Thin SOI MOSFET's and Practical Guideline for ESD-Protection Device Design

Author

Shiwaya, Yoichi and Omura, Yasuhisa

Subjects
equivalent circuit model, 関西大学, snap-back, Hardware_INTEGRATEDCIRCUITS, electrostatic discharge, Kansai University, Hardware_PERFORMANCEANDRELIABILITY, SOI MOSFET, Hardware_LOGICDESIGN, parasitic bipolar action
Abstract

This paper proposes a compact equivalent-circuit model for the snap-back phenomenon in ultra-thin SOI MOSFET's. The model can be used in simulations of I/O circuits with ESD-protection devices. The model is more simple than past models, but it successfully reproduces the snap-back response. With the aid of many simulations, we propose a guideline for snap-back SOI MOSFET device design. Useful parameter-sensitivity equations for device characteristics are given for practical device designs.

Published
2007

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