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This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF $((2^{2})^{2})$ , is reduced. The squaring and multiplication with constant $\lambda $ in GF $((2^{2})^{2})$ are combined and optimized as well. Moreover, the multiplicative inversion in GF $((2^{2})^{2})$ is manually optimized. Furthermore, the S-box and inverse S-box are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.

A new motion estimation method and its hardware implementation are presented in this paper. In this method, all the frames are firstly gray coded. After that, the two most significant bits from the...

Active contour segmentation is an important stage in image analysis applications. In this article, an improved region based active contour segmentation is proposed. The proposed active contour model speeds up the contour convergence by up to 40% while maintaining the advantages of a local region based active contour model by reducing the number of iterations. Moreover, we propose a low-complexity pipelined VLSI architecture for improved region based active contour model targeting FPGA and 90 nm ASIC platforms. The proposed pipelined design offers an increased speed of operation. Its complexity is independent of the size of image.

Conventionally, decimation-in-time (DIT) data-flow-graph (DFG) is used to obtain computing structures for discrete Hadamard transform (DHT). The fixed-width structures based on conventional approach, however, offers a marginal bit-saving and introduces relatively more truncation error. In this paper, we have derived decimation-in-frequency (DIF) DFG for DHT which is more convenient for approximation using truncation than the DIT-DFG. To achieve higher bit-saving with relatively less truncation error, we propose an efficient truncation model comprising of pre-truncation ( $\delta $ ) and post-truncation ( $\gamma $ ). Also, we present a logic optimized adder-subtractor design customized for DHT structure. Using the proposed truncation model, we have three variants of proposed structures for parallel computation of 2D DHT. The proposed structure-2 for DHT size $N=8$ , word-size $w=8$ , and approximation $(\delta _{1}=2, \gamma _{1}=1, \delta _{2}=2, \gamma _{2}=1)$ involves nearly 38% less area-delay-product (ADP) and 46% less energy per sample (EPS), and calculates outputs with almost the same accuracy as the existing fixed-width structure based on post-truncation. For the same word-size and $N=16$ , the proposed structure-2 for approximation $(\delta _{1}=2, \gamma _{1}=2, \delta _{2}=2, \gamma _{2}=2)$ involves nearly 36% less ADP and 44% less EPS than the existing structure and calculates outputs with the same accuracy. We have observed that reconstructed images obtained using the proposed structure-2 are less by 7 dB and 2 dB PSNR than those obtained using the existing fixed-width structures for $N=8$ and 16, respectively.

The analysis carried out in the article shows the possibility of creating a problem-oriented VLSI, fabricated according to the technological standards of 28 nm or less, for at least one family of digital signal processing problems using similar computing nodes in structure. The use of distributed arithmetic allows one to apply a technique based on performing only those multiplication steps for which non-zero digits are set in the corresponding positions of the filter coefficients. Therefore, the performance of 200 nodes executing 2 steps at 1 GHz is equivalent to approximately 80 GMAC/s/mm2 for 16-bit coefficients. The VLSI architecture view opens up the possibility to study the effectiveness of implementing other families of tasks and refine the architectural parameters for their implementation. The proposed functionality of VLSI computing nodes allows them to be used in various fields of technology, which potentially increases the need for the release of such VLSI.

In the recent years the computational units are optimized to reduce the computation time. Multiplier is an electronic circuit used in digital electronics and has a significant role in vlsi applications. The 4:2 compressors have a flexibility of switching between exact and appropriate operating modes. In the appropriate mode the dual quality compressors provides higher speeds and consumes low power. Using these compressors in the structures of parallel multipliers provides configurable multipliers whose accuracies (as well as their powers and speeds) may change dynamically during the runtime. The efficiencies of these compressors are used in another type of multiplier and are evaluated in 45 nm standard CMOS technology. By comparing the parameters of this multiplier with those of appropriate multipliers, the results indicate a better in almost all the aspects.

This paper proposes the robust proportionate adaptive filtering algorithms and their respective efficient very large-scale integration (VLSI) architectures for sparse system identification under impulsive noise, several types of algorithms are combined to obtain optimum results. Here, we rendered a relative analysis on these algorithms and the algorithms are mapped on to the hardware to show that the improvement is obtained with respect to convergence rate and hardware complexity of VLSI architectures and has negligible hardware overhead with improved robustness. Good performance and convergence rate is obtained by combining the delayed μ-law proportionate (DMP) and least mean logarithmic square (LMLS) algorithms i.e. delayed µ-law proportionate least mean logarithmic square (DMP LMLS). Robust proportionate adaptive filter is coded in system verilog and synthesized using cadence genus compiler with 90 nm technology library.

This paper introduces an FPGA implementation of a pseudo-random number generator (PRNG) using Chen’s chaotic system. This paper mainly focuses on the development of an efficient VLSI architecture of PRNG in terms of bit rate, area resources, latency, maximum length sequence, and randomness. First, we analyze the dynamic behavior of the chaotic trajectories of Chen’s system and set the parameter’s value to maintain low hardware design complexity. A circuit realization of the proposed PRNG is presented using hardwired shifting, additions, subtractions, and multiplexing schemes. The benefit of this architecture, all the binary multiplications (except [Formula: see text] and [Formula: see text] operations are performed using hardwired shifting. Moreover, the generated sequences pass all the 15 statistical tests of NIST, while it generates pseudo-random numbers at a uniform clock rate with minimum hardware complexity. The proposed architecture of PRNG is realized using Verilog HDL, prototyped on the Virtex-5 FPGA (XC5VLX50T) device, and its analysis has been done using the Matlab tool. Performance analysis confirms that the proposed Chen chaotic attractor-based PRNG scheme is simple, secure, and hardware efficient, with high potential to be adopted in cryptography applications.

This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the $N$ -point DCT by means of two $N/2$ -point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware re-usability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion loss es, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel.

Stochastic computing (SC) has been applied on the implementations of complex arithmetic functions. Complicated polynomial-based approximations lead to large hardware complexity of previous SC circuits for arithmetic functions. In this paper, a novel piecewise approximation method based on Taylor series expansion is proposed for complex arithmetic functions. Efficient implementations based on unipolar stochastic logic are presented for the monotonic functions. Furthermore, detailed optimization schemes are provided for the non-monotonic functions. Using NAND and AND gates as main computing elements, the optimized hardware architectures have extremely low complexity. The experimental results show that a broad range of arithmetic functions can be implemented with the proposed SC circuits, and the mean absolute errors can achieve the order of 1 × 10-3. Compared with the state-of-the-art works, the approximation precision for some typical functions can be increased by more than 8× with our method. In addition, the proposed circuits outperform the previous methods in hardware complexity and critical path significantly.

The FFT is enumerate is DFT and DFT is enumerate is consecutive way, it accomplishes continuous application with constant preparing when the information is persistently taken care of through the processor. Included paper, joined is radix-2 butterfly (R 2 B), R 4 B & R 8 B components based single path delay feedback (SDF) and modified carry select adder (MCSLA) technique, for diminishing the computational stages and for decreasing the equipment use than the R2B and R 4 B FFT. The implemented SDF technique has single delay commutators at one stage without exception. N/2 point is consecutive controlled in consequence of delay component. The proposed technique has less number of multipliers and the more modest number of computational stages and butterfly components than the Radix-2 & 4 FFT.

The main objective of this work is to suggest an FIR filter for convolution-based DWT in image processing. Image processing using filters mainly suffers from the delay caused by the multiplier unit. Herewith, we have proposed booth multiplier-based MAC architecture for the design of FIR filter. Hence, the overall system achieves maximum speed improvement of 13.83% and area reduction by 22.39%. This work assures that the performance improved VLSI architecture for image processing with DWT techniques.

Through theoretical analysis, the calculation method of dual basis multiplication in GF (28) field based on CCSDS Berlekamp is given. Based on this calculation method, a VLSI architecture for parallel multiplication and serial operation in circuits is proposed. At the same time, the hardware resource occupation and the timing performance of each VLSI architecture are analyzed in detail.

This work presents an efficient NLMS-based VLSI architecture to extract the fetal electrocardiogram (FECG) and detect the fetal heart rate (FHR), using the adaptive filter strategy. The efficient NLMS-based architecture herein investigated can robustly cancel the high-noised mother-related ECG signals, enabling the FHR measurement. We used the Improved Fetal Pan and Tompkins Algorithm (IFPTA) to detect fetal R-peak and calculate the FHR. Our NLMS-based VLSI architecture effectively detects the R-peaks in the extracted FECG with 93.2% accuracy with the only 2.4 mW of total power dissipation.

Guided image filtering has been applied widely for increasing demand of high performance filtering, especially for real-time image/video processing. Gradient guided filter improves the filtering quality, reducing the halo-artifacts problem due to its edge-aware characteristics. However, the gradient guided filter algorithm has high computation complexity and the computation involves global pixels, which hinder its VLSI implementation for real-time full-HD application. This work addresses these issues and a VLSI architecture is proposed for the gradient guided image filter. Several design techniques are developed and used in the design to achieve high computation speed and high throughput. A seamless dataflow is proposed for the complete system that consists of three main processing stages, specifically the preprocessing stage, the linear coefficient computation stage and the output stage. The preprocessing stage applies a down-sampling technique with a large sampling rate to reduce computation cost in terms of circuit size, processing time and power consumption. The global parameter values are quickly derived with reasonable good global information maintained so that the quality of the filtering results are not sacrificed when these values are applied in the subsequent two stages. The linear coefficient computation stage contains the most complex computations such as square root, division and exponential function. Down-sampling technique is applied with a sampling rate lower than in the preprocessing stage so as to balance the computation cost and filtering accuracy. In addition, the intensive arithmetic computation modules that dominate the critical path delay are redesigned by using adequate approximated operations. Specifically, novel non-iterative dividers are developed to replace original dividers for reducing delays in the critical paths. With the proposed non-iterative division,the quotient of the division is modeled as a normalized curved surface. The curved surface is partitioned into small regions and approximated by smaller planes for efficient hardware implementation. Curve fitting method and mixed integer linear programming method are adopted and evaluated for local optimization of the approximation errors. In this way, the dividers are implemented with only simple arithmetic operations and a small look-up table. As a result, the operation is fast and the approximation errors are optimized while satisfying the accuracy requirement. The other intensive computation, the exponentiation function, is also simplified by piecewise linear approximation, and implemented with only shifters and adder trees. As such, the approximated computations are used to improve the computation performance and simplify the designs of the complex arithmetic modules. The output stage employs parallel processing and operates at a frequency 16 times higher to restore the filtering results to its original full frame size. The linear coefficients obtained from the downsampling stage are applied concurrently to all the 16 pixels in the window that the coefficients are computed for. As a result, not only the original image size is restored, the quality of the filtering results is maintained and high throughput is achieved at the same time. Based on the STM 65nm CMOS technology, the implementation result shows the proposed VLSI architecture for the gradient guided image filter is able to support Full-HD image filtering at a throughput above 150 frames per second, achieving high throughput, small size and low power consumption comparing to the existing VLSI design for the original guided image filtering. This thesis describes the proposed VLSI architecture, the details of its design, the designs of the non-iterative dividers and the design of the piecewise linear approximated exponential function. The qualitative and quantitative analysis of the impact of the approximations on the filtering results and the performance comparisons of the proposed designs and the existing designs are included. Doctor of Philosophy (EEE)

Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm. Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural properties. The AES architecture with the enhanced mix column to be proposed with reduced number of transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding the VLSI design environment. The simulation results of the proposed structure are performed with the minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS technology based AES Algorithm is integrated into the backend based chip technology. &nbsp

High Efficiency Video Coding (HEVC) is the latest video standard developed by the Joint Video Exploration Team. HEVC is able to offer better compression results than preceding standards but it suffers from a high computational complexity. In particular, one of the most time consuming blocks in HEVC is the fractional-sample interpolation filter, which is used in both the encoding and the decoding processes. Integrating different state-of-the-art techniques, this paper presents an architecture for interpolation filters, able to trade quality for energy and power efficiency by exploiting approximate interpolation filters and by halving the amount of required memory with respect to state-of-the-art implementations.

Fractional motion estimation (FME) is used in all the latest video coding standards to reduce the bit-rate. In FME, Hadamard transform (HT) is used to calculate total distortion. HT helps to find the best-matched candidate block. Unlike the earlier video coding standards, HEVC supports the variable size of HT such as 2 × 2, 4 × 4, 8 × 8, 16 × 4 and 4 × 16. Therefore, the development of an efficient scalable VLSI architecture for HT compatible with HEVC is a challenging task. In this paper, we have proposed a scalable architecture for HT which supports all the sizes of HT adopted by HEVC. Simulation and synthesis of the proposed architecture are carried out using standard 90 nm Technology. Simulation results show that the proposed architecture can process 4K video sequences and occupies only 0.2517 mm2of the area. The proposed architecture consumed 19.0225 mW of power for the operating frequency of the 250 MHz.

In the High Efficiency Video Coding (HEVC), a variety of CU sizes and intra prediction modes significantly improve coding efficiency, but also bring higher computational complexity. This paper proposes a new compact VLSI architecture for HEVC intra prediction, which is geared towards 8K video decoding. It supports all the transform unit (TU) sizes and 35 HEVC intra prediction modes. First, this paper introduces a TU-oriented intra predictor with a throughput of 32 pixels, which can be newly arranged with the TU size. It can be a line of 32 pixels, two lines of 16 pixels, 4 lines of 8 pixels or four lines of four pixels. This TU-oriented architecture allows intra-prediction and inverse discrete cosine transform (IDCT) to be computed in parallel, removing the memory between them. In addition, a horizontal and vertical line buffer for reference sample is proposed, which only cost 0.8K bit and is implemented by register files with SRAM-free. Finally, to further reduce hardware consumption, multipliers can be shared in the prediction. The implementation result shows that the compact architecture supports 8K video application and costs 66.2K logic gates, which is synthesized with the TSMC 65nm process under 400MHz.

With the increasing demand in electronic gadgets expecting better video quality for multimedia applications, various coding standards evolved for the past two decades and optimization on the architectures of the various modules used in the video codec is most popular. In this paper, an efficient architecture for deblocking filter used to smoothen the pixels of the decompressed video data is proposed, which utilizes both pipelining and parallelism. The filtering process follows a sequential order as filtering vertical edges of luma block and chroma block followed by the horizontal edges of the luma block and chroma block. Three pipeline stages are used and four edges, either vertical or horizontal are filtered in parallel. Internal buffers which hold the sub-blocks read from the external frame buffers are accessed in a ping pong fashion to filter the adjacent sub-edges and thus reducing the external memory access cycles. Due to parallelism with novel edge filtering order, self-transposing mechanism, and ping pong buffer access, the throughput is increased. The proposed quad parallel edge deblocking filter architecture is implemented using Synopsys 90 nm library. It achieves a target area of 19.8 K and can process a Macro Block in 58 clock cycles.

Line coding is used to tune the wave form based on the properties of the physical channel. The wave form is tuned in voltage or current or photon levels for the proper digital data transport. Bi-Phase Mark Coding (BMC), Bi-Phase Space Coding (BPSC) and Phase Coding (PC) are used as Line coding techniques. Most of the existing systems discuss about any one of the coding techniques among BPSC and PC. Limited number of systems discusses about BPSC and PC generation and degeneration operations together. The first objective of the proposed work is to design BMC, BPSC and PC techniques Generation and Degeneration operation in a single system. The second objective is to reduce the area and power consumption by modifying the number of MOS devices used for the system design and by adjusting the width of the MOS devices. The system is designed using Cadence® Virtuoso Schematic Editor at 180 nm technology. Simulation is done using Cadence® Virtuoso ADE and the Layout is designed using Cadence® Virtuoso Layout Suite XL. The proposed system requires 59 transistors and occupies 1632.88 µm2. Required power can be reduced up to 33% by using any one of the suitable coding among BMC, BPSC and PC based on the properties of the input data signal. If the input data is having equal possibility of high and low level signals, PC technique will be suitable for power reduction. If the high level beats the low level, BPSC technique will be suitable. If the low level beats the high level, BMC technique will be suitable.

In H.265/high efficiency video coding (HEVC) encoding, rate distortion optimization (RDO) is an important cost function for mode decision and coding structure decision. Despite being near-optimum in terms of coding efficiency, RDO suffers from a high complexity. To address this problem, this paper presents a fast RDO algorithm and its very large scale implementation (VLSI) for both intra- and inter-frame coding. The proposed algorithm employs a quantization-free framework that significantly reduces the complexity for rate and distortion optimization. Meanwhile, it maintains a low degradation of coding efficiency by taking the syntax element organization and probability model of HEVC into consideration. The algorithm is also designed with hardware architecture in mind to support an efficient VLSI implementation. When implemented in the HEVC test model, the proposed algorithm achieves 62% RDO time reduction with 1.85% coding efficiency loss for the “all-intra” configuration. The hardware implementation achieves 1.6 × higher normalized throughput relative to previous works, and it can support a throughput of 8k@30fps (for four fine-processed modes per prediction unit) with 256 k logic gates when working at 200 MHz.

Due to the sparse multipath characteristic of the channel, millimeter wave (mmWave) channel estimation can be treated as a sparse signal recovery problem. By exploiting the channel sparse characteristics with compressive sensing (CS) theory, sparse signal recovery algorithms can be used for channel estimation. Orthogonal matching pursuit (OMP) algorithm is one of the most popular CS reconstruction algorithms. Hence, in this paper, we present OFDM-based mmWave sparse indoor channel estimation using the OMP algorithm. However, the computational effort for OMP remains high, even for problems of moderate size in real-time applications. Hence, a new VLSI architecture for mmWave channel estimation using the OMP algorithm is designed and simulated using Xilinx 15.4 Vivado HLS simulator in this paper. Our empirical results illustrate the efficacy of the proposed approach.

This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier-based double throughput MAC.

In this paper, an efficient symbol-deinterleaver architecture compliant with the digital-video-broadcasting (DVB) standard is proposed. By partitioning the entire symbol buffer into four separate parts with a special low-conflict access control strategy, the symbol deinterleaver can be implemented with four-bank single-port on-chip memory blocks with slight overhead. The experimental result shows that 30% savings of hard-ware cost can be achieved compared with the conventional double-buffer approach. In addition, a lookahead online circuit of a symbol permuta-tion-address generator is also proposed, which can provide the required permutation addresses every cycle to avoid either the use of a lookup table or an extra temporary buffer. Being the major part of the entire DVB forward-error-correction decoder, the proposed symbol deinterleaver can contribute a great saving of the overall decoder cost.

Performing the image compression over the resource constrained hardware is quite a challenging task. Although, there has been various approaches being carried out towards image compression considering the hardware aspect of it, but still there are problems associated with the memory acceleration associated with the entire operation that downgrade the performance of the hardware device. Therefore, the proposed approach presents a cost effective image compression mechanism which offers lossless compression using a unique combination of the non-linear filtering, segmentation, contour detection, followed by the optimization. The compression mechanism adapts analytical approach for significant image compression. The execution of the compression mechanism yields faster response time, reduced mean square error, improved signal quality and significant compression ratio performance.

2-D-to-3-D conversion is one way to make full use of 2-D contents to produce 3-D contents. Real-time 2-D-to-3-D conversion is required for 3-D consumer electronic devices, which demands fast processing speed especially for high-definition videos. In this paper, we propose a reconfigurable VLSI architecture for real-time 2-D-to-3-D conversion. Two different depth-retrieval methods are implemented in this architecture in order to support the choice of a best method or combination of different methods. The proposed architecture can also support different resolutions (4K, 1080p, and 720p) and the original view can be configured as either left view or right view. In order to overcome the problem of “Memory Wall”, we propose a data reuse method to reduce memory traffic for the proposed architecture so that the overall performance is improved to realize real-time conversion. The experiment result shows that the implemented 2-D-to-3-D architecture can achieve state-of-the-art throughput (4K@30f/s).

In this work, VLSI architectures with less delay/area for lifting based DWT are proposed.The proposed logic used for area efficient DWT is to perform the whole operation with one processing element.The proposed logic used for delay efficient DWT is to perform the whole operation with multiple processing elements in parallel.In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. In this paper, high performance VLSI architectures for lifting based 1D and 2D-Discrete wavelet transforms (DWTs) are proposed. The proposed logic used for area efficient lifting based DWT is to perform the whole operation with one processing element. Similarly, the proposed logic used for delay efficient lifting based DWT is to perform the whole operation with multiple processing elements in parallel. In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. The proposed and existing lifting based 1D and 2D lifting based DWTs are implemented with 45źnm technology. The results show that the proposed designs achieve significant improvement compared with existing architectures. For example, 9-point 2-parallel proposed (9, 7) single level 1D-DWT achieves 33.5% of reduction in total cycle delay compared with direct form. Similarly, 9-point single PE proposed (9, 7) single level 1D-DWT achieves 59.8% and 75.5% of reduction in total area and net power over direct form respectively.

The article considers the VLSI architecture intended for streaming data processing using a configurable path based on sequential distributed arithmetic. The development of specialized VLSIs is advisable if there is a need for serial production of devices, and the domain of application of such VLSIs decreases as the capabilities of the CPU, GPU and FPGA expand. The alternative approach is to build configurable VLSIs that can efficiently perform computations in related applications. The solution under consideration is focused on performing stream operations, including FIR filters and other tasks based on the operation “multiplication and accumulation”, for example, neural networks and deep learning algorithms. The architecture provides for compliance with the GALS (Globally Asynchronous, Locally Synchronous) approach, which allows placing many independent computing nodes in the VLSI. The characteristics of VLSI were evaluated and the areas of preferred application of the considered architecture were considered.