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Ultra-low-power circuits that can work under a low-voltage supply are in great demand in future wearable biomedical applications, which tend to be integrated with low-output-voltage energy harvesting devices. In this paper, we present a low-voltage low-power continuous-time low-pass filter (CT-LPF), which is indispensable in biomedical systems. When a low-voltage supply is used, it is necessary to make the output quiescent voltage ( $\text{V}_{\mathrm {Q}}$ ) stable in the LPF, otherwise the dynamic range will be reduced. Conventional Source-follower (SF) based topologies can achieve ultra-low-power consumption. However, the difference of the input and output $\text{V}_{\mathrm {Q}}$ is sensitive to process and temperature variations. In this work, a complementary SF based topology with a bulk-common-mode-feedback (B-CMFB) circuit is proposed to keep the output $\text{V}_{\mathrm {Q}}$ tracking the input $\text{V}_{\mathrm {Q}}$ and immune to the process and temperature variations. A 4th-order LPF using the proposed topology has been implemented in a standard $0.18~\mu \text{m}$ CMOS process, which achieves a power consumption of only 3.69-nW under a 0.5-V voltage supply with a bandwidth of 200 Hz. Measurement results show that the input-referred noise is $91.9~\mu \text{V}_{\mathrm {rms}}$ . The IIP3 is 5.0 dBm and the dynamic range (DR) is 48.5 dB. The active chip area is only 0.074 mm2. The proposed LPF achieves both ultra-low power consumption with a 0.5-V supply and a stable output $\text{V}_{\mathrm {Q}}$ immune to process and temperature variations, which is suitable for low-supply-voltage biomedical systems.

The investigation of high-efficiency electrodes is essential for the energy conversion/storage devices. In this work, mesoporous two-dimensional Ni-Co hydroxide nanosheets stabilized by BO

This letter presents a CMOS reverse received signal strength indicator (reverse-RSSI) based logarithmic power detector (PD). A capacitor attenuation array and unbalanced source-coupled rectifiers are utilized to constitute the reverse-RSSI architecture, which greatly increases the maximum detectable power. Two auxiliary capacitors in the rectifier are introduced to improve linearity at high input power dramatically. The PD with 0.4–5-GHz operating frequency can be fully integrated and has stable and reliable performance according to multiple tests. Measurement results show that the maximum detectable power achieves +35 dBm and dynamic range reaches 45 dB with ±1-dB linearity error. The proposed PD is implemented in a standard 180-nm CMOS process with 0.085 mm2 core area. The total static power consumption is 0.78 mW with a 3.3-V supply voltage.

A high-resolution digitally controlled oscillator (DCO) for frequency-modulated continuous-wave radar applications is presented in this brief. The proposed DCO utilizes a variable inductor and linearization correction technique, and cooperates with the multi-stage frequency multipliers to achieve frequency sources at 2.9, 5.8, and 11.6 GHz simultaneously on a single chip. The demonstration of the proposed DCO and frequency multipliers was fabricated in 1P10M 40-nm CMOS technology. Measurement results show that the frequency resolution of the DCO achieves 0.73 to 1.3 kHz over a frequency range of 16.8%, from 2.5 to 2.96 GHz. The phase noise at 1-MHz frequency offset is −127.3 dBc/Hz with 15-mW power consumption. The chip occupies 0.73 mm2, while the proposed DCO occupies a core area of 0.31 mm2.

A Gm-compensated 46-101 GHz broadband power amplifier (PA) for high-resolution FMCW radars is presented in this paper. For bandwidth (BW) expanding, a Gm compensator-based negative feedback chain is applied to the PA, compensating the large gain ripple caused by a high-k transformer (TF)-based ultra-wideband interstage matching network (IMN). Based on the proposed Gm-compensated technique, a flat and ultra-wideband power gain of the PA can be obtained with the high-k TF-based IMN. The proposed PA achieves a 55-GHz BW without additional area overhead and efficiency loss. 74.8% of the fractional BW is obtained with

A Quadrature/Polar hybrid digital transmitter architecture (HB-TX) is proposed in this paper, which consists of a main digital power amplifier (DPA), an auxiliary DPA, and a low-bit phase selector. In the proposed HB-TX, coarse polar modulation is realized by combining the main DPA and a low-bit selector, while a fine quadrature modulation is realized by the asymmetrical quadrature recombination of main and auxiliary DPAs in a small range. Through coarse and fine modulation, the HB-TX realizes fast signal modulation and does not require high-speed and high-resolution phase modulator. With the coarse polar modulation, the HB-TX achieves high efficiency which is close to that of polar transmitter and no longer suffers from 3 dB back-off. Since the asymmetry of two-path DPA arrays improves the isolation between two channels, local oscillators (LOs) with 50% duty cycle is employed to further improve the HB-TX's efficiency. Simulation results show that the HB-TX with a 4-bit selector achieves 23.7-dBm peak output power with 39.2% peak power added efficiency (PAE). When modulating a 64-QAM signal with 80-Msym/s symbol rate and 6.5-dB peak average power rate (PAPR), the HB-TX improves the average drain efficiency from 16.3% (achieved in quadrature transmitter) to 22.2% The average output power that is delivered by the HB-TX is 17.6-dBm with 17.4% average PAE, while the error vector magnitude (EVM) is -35.87 dB.

An 81–99 GHz tripler for wireless transceiver LO generation is presented in this paper. To suppress the fundamental signal and enhance the 3rd harmonic, the inversion signal is applied to the gate of the cascading transistor of the push-push differential pair. A capacitor is connected to the source and drain of the cascading transistor to further suppress the fundamental signal. Without additional filters, the tripler achieves more than 40 dBc of fundamental suppression with an even harmonic suppression of up to 60 dBc. The tripler reaches an output power of −2.6 dBm (4-dBm input) at 91.5 GHz with a 20% bandwidth of from 81 to 99 GHz. The core area of the chip occupies only 190 μm×530 μm in TSMC 40-nm CMOS process and consumes 28.2 mW.

This paper presents a CMOS fully-integrated temperature sensor based on a relaxation oscillator for IoT applications. To reduce power consumption, this sensor utilizes the half-period pre-charge compensation relaxation oscillator and uses a time-to-digital convertor (TDC) instead of analog-to-digital convertor (ADC) to count. Besides, the current distribution circuit is employed to improve temperature accuracy. The proposed sensor is implemented in 0.18 µm CMOS and occupies an area of 0.11 mm2. Measurement results show that the temperature sensor achieves an inaccuracy of −0.3/+0.27 °C across −15°C to 65°C after 2-point calibration. The chip consumes 1.3 µW at 27°C with a 650 mV voltage supply.

This paper presents a fractional-N all digital phase locked loop (ADPLL) using a retiming high linear digital phase interpolator (DPI), which is free from pre- and background-calibration. The DPI utilizes a charge-sharing effect insensitive charge-based structure to improve the linearity. Designed in a 40-nm CMOS technology, the proposed DPI achieves 9-bit resolution, 0.3ps integral nonlinearity (INL) and 0.083ps differential nonlinearity (DNL). The proposed ADPLL achieves −118 dBc/Hz in-band phase noise at 1MHz and −93.9dBc fractional spur with the 0.3ps nonlinearity of DPI.

A low power highly reconfigurable analog baseband (ABB) for internet of things (IoT) application is presented in this paper. To overcome the problems caused by low intrinsic gain in deep sub-micron CMOS technology, thick gate-oxide transistors technique and active balun techniques are utilized to boost the voltage gain of the operational amplifier. Moreover, a smart common-mode feedback bias circuit is used to make the operational amplifier (OPAMP) robust to process variations and mismatch. The presented ABB provides a maximum gain of approximately 80 dB with a step of 1dB and covers a cutoff frequency range from 1.25 MHz to 20MHz. The ABB has been implemented in 40 nm CMOS and the simulation result shows that it consumes 9.8mW power from a 1.5V supply voltage with a core die area of 0.26mm2.

In this paper, a low power 0.4-1 GHz receiver front-end (RX-FE) with an enhanced third-order-harmonic-rejecting series N-path filter (3rd-HRSNPF) is proposed. The 3rd-HRSNPF provides sufficient third order harmonic rejection (HR3) to eliminate the harmonic rejection mixer (HRM). The receiver front-end has been implemented in a 40 nm CMOS technology. Simulation results show that it achieves a HR3 of 53 dB without HRM in case of 6% duty-cycle error and 0.5° phase error. Operating from 0.4–1 GHz, its power consumption and double-sideband noise figure (DSB NF) are only 8.2–9.9 mW and 3.0–3.2 dB, respectively.

An on-chip broadband self-interference canceller based on the electrical balance of hybrid transformers is proposed in this work. A variable inductor based on-chip balanced impedance network is utilized to match the actual antenna impedance varying with frequency. In order to achieve broadband electrical balance, an auxiliary quadrature digital transmitter is used to compensate variations of the antenna impedance with frequency. The proposed technique is demonstrated in a standard 130 nm CMOS 1P8M process and the chip occupies 4.84mm2. The simulation results show that the demonstration achieves isolation of more than 60 dB over a 25 MHz bandwidth with 23 dBm transmitter output power at 2 GHz.

This paper proposes a 2.4 GHz ultra-low power pseudo-backscatter modulator with an integrated directional coupler for wireless sensor network applications. In order to improve the performance of backscatter modulator for multilevel modulation, an integrated directional coupler is employed to isolate the radio frequency carrier wave from the modulated signal. As a result, the carrier wave can be modulated in radio frequency domain independently without being affected by reflection coefficient of a conventional backscatter modulator. For further reducing power dissipation, the modulator only employs buffers for output and implements modulation by passive circuits. The proposed modulator is demonstrated in a standard 40 nm CMOS 1P10M process and it achieves 64-QAM modulation at 3 Mb/s data rate by consuming only 43.2 μW with a supply voltage of 0.8 V.

In this paper, a novel silicon-controlled rectifier (SCR) structure is proposed to protect a radio-frequency (RF) power amplifier (PA) from electrostatic-discharge (ESD) damages. With a distinguished feature of an imbedded Deep N-well (DNW) area beneath the P-well/N-well regions, the novel SCR is demonstrated to be superior to the conventional SCR in terms of relatively low trigger voltage (13.3V) and high holding voltage (7 V). The new device can be realized in SMIC 0.18μm RF technology without requiring extra layout area. The operational mechanism of the new device structure is investigated, and the effect of the additional DNW region on the SCR's I-V characteristics is analyzed by TCAD simulation.

In this paper, a novel combinational access topology of Tunnel FET (TFET) SRAM is proposed for ultra-Low Power applications. Since forward p-i-n current of TFET could cause serious damage to SRAM circuit performance, the proposed topology can avoid the forward bias applied to the p-i-n junction, thus increasing SRAM cell read and hold static noise margin (SNM) and decreasing its static power consumption dramatically. At 0.6 V supply voltage, the combinational access TFET SRAM topology presents 26% hold SNM larger than traditional TFET SRAM topologies, 8 orders of magnitude lower static power consumption, and 2 order of magnitude lower power delay product, demonstrating its great potential for ultra-low power applications.

A 12-bit 2.5GHz digital-to-time converter (DTC) for high resolution and high linearity applications is presented in this paper. The DTC is segmented into a 4-bit coarse stage and an 8-bit fine stage. The proposed fine stage utilizes parasitic-insensitive charge-based (PICB) phase interpolator (PI) with significant improvement in linearity. The PICB PI outputs 50% duty cycle differential clock and its performance is insensitive to parasitic effect. The DTC is designed in 40nm CMOS technology and consumes 7.1mW with a 1.1-V supply voltage. Simulation results show that the peak integral nonlinearity and differential nonlinearity are 0.37ps and 0.085ps, respectively.

This paper presents a low power SAW-less 2.4-GHz receiver for short-range communications. To ensure sufficient out-of-band (OOB) linearity for SoC existence, a LC matched series N-path filter based receiver topology is proposed. The radio frequency input is followed by the LC matched series N-path filter, which provides sufficient ultimate rejection when consuming less power than conventional N-path filters. An on-chip inductor and a capacitor are utilized to achieve input matching and improve the NF. Implemented in TSMC 40nm LP process, the chip occupies an active area of 0.312 mm2. Simulation results show that the receiver consumes 2.2 mW from 1.1V supply voltage with a NF of 6.3 dB (with the on-chip inductor) and a voltage gain of 38.4 dB. The baseband achieves a third order filtering response with 1.5 MHz bandwidth. The OOB 1-dB compression point is +7 dBm and the OOB IIP3 is +22 dBm.

This paper presents a MICS/ISM band receiver for ultra-low-power applications with a passive RF front-end. A shunt passive mixer along with low input capacitance amplifiers is introduced to decrease the large load capacitor and minimize power consumption of the Local Oscillator (LO) buffers without significant noise figure (NF) degradation. Measurement results show that the receiver consumes 89 μW from 1 V supply voltage with a NF of 7.5 dB and a voltage gain of 47.6 dB. S11