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This paper presents the design and implementation of a direct amplitude (AM) demodulator using artificial neural network (ANN) on field programmable gate array (FPGA), which enables direct demodulation of modulated carriers to baseband waveforms. This direct AM demodulator introduces a novel approach by eliminating the need for intermediate frequency (IF) conversion, leveraging a neural network instead of a traditional analog local oscillator and mixer. Eliminating the IF stage allows for the use of wider bandwidth, supporting modern wideband communication systems. By omitting these conventional components, the proposed ANN-based direct AM demodulator reduces system noise, thereby enhancing fidelity. The proposed ANN-based direct AM demodulator uses a pre-processing technique to generate the carrier signal digitally at the input of the ANN enabling effective handling of high-frequency modulated signals. The implementation of the proposed ANN-based direct AM demodulator targets the XC7VX690T Virtex-7 FPGA platform, validated using Xilinx Vivado simulations. The ANN's adaptability across different carrier frequencies enhances hardware reusability and resource efficiency. The ANN-based direct AM demodulator implemented on FPGA is faster than the ANN implemented using the C++ based fast artificial neural network (FANN) library which reduces the overall processing time and allows the operation of higher carrier frequencies. Results demonstrate the demodulator's capability to process sine and square waves across a wide frequency range: modulating frequencies from 2.5 MHz to 20 MHz and carrier frequencies from 50 MHz to 200 MHz supporting a maximum bandwidth of 40 MHz. The proposed demodulator operates efficiently at a maximum carrier frequency of 200 MHz, with a sampling frequency of 1.66 GHz. Experimental results confirm the ANN's robust performance across varying signal-to-noise ratios (SNRs) from 10 dB to 100 dB, showcasing MSE values ranging from 0.06 to 0.000001. Further to add, no noise filter is required after an SNR of 30 dB. The design is achieving only 16% amplitude distortion, thus offering an acceptable fidelity. The proposed demodulator consumed only 63.25% of LUT slices for a single hidden layer and 82.36% of LUT slices for two hidden layers ANN implementations on the specified FPGA board. DSP48E1 units used are 37.71% for the single layer and 60.21% for the multi-layer. The processing speed of the ANN based direct AM demodulator implemented on FPGA is 60.125, and 44.65 at f c of 50 MHz, and 200 MHz respectively. Overall, this ANN-FPGA based approach represents a significant advancement in AM demodulation technology, offering enhanced adaptability and performance compared to traditional methods. [ABSTRACT FROM AUTHOR]

Electric vehicles have seen substantial growth in recent years in the emerging economies of the world. The current market scenario of E-vehicles is dominated by PMSM or BLDC motors due to their higher torque-to-power density, and efficiency with added performance metrics of the motor. However, the higher capital cost of permanent magnets makes the motor designers to consider an alternative to magnetic motors, the so-called Switched Reluctance Motors (SRM). With proper FEM analysis and controller design, if SRMs can able to achieve the performance metrics of a PMSM/BLDC, it will be a breakthrough in the automotive sector with affordable prices. Based on the aforementioned facts, this research work focuses on SRM as a viable alternative to the existing PMSM/BLDC motor. The work concentrates on the design and development of an 8/6 SRM for a Tri-wheeler E-vehicle application. The designed motor is fabricated, tested and controlled by WAVECT, an FPGA-based real-time digital controller which is used to control the commutation of the 8/6 SRM. The yielded response satisfactorily proves that the designed 8/6 SRM can be effectively used for the Tri-wheeler E-vehicle application, thereby paving the way for sustainable energy conservation in the automotive sector. [ABSTRACT FROM AUTHOR]

The purpose of this work is to investigate the construction of fuzzy embedded control systems combining fast execution and parallel processing capabilities provided by Field Programmable Gate Arrays (FPGAs) and Reconfigurable Inputs/Outputs (RIO) chips. A fixed-point fuzzy controller is developed and implemented on a fast mechatronic system with high-speed control and high channel count on an FPGA target. This paper provides a brief introduction to deploying Fuzzy Logic Control (FLC) methods using RIO-FPGA technology. It suggests a technique for implementing the three stages that constitute the FLC and the PD-like FLC and PID-like FLC structures into practice. Controllers with 1 and 2 degrees of freedom are developed and tested experimentally. Parallel loops, key challenging advantage of LabVIEW programming, are utilized for decoding feedback signals, generating pulse trains for actuator's drivers and for calculation of control gains. An NI-SbRIO board that combines deployable devices with a real-time processor, a re-configurable FPGA, and analogue and digital input–output ports is used. The experimental work demonstrates the significant enhancement of implementing reconfigurable embedded fuzzy control upon such mechatronic systems. [ABSTRACT FROM AUTHOR]

Field Programmable Gate Arrays (FPGAs) have garnered significant attention in the development and enhancement of target identification algorithms that employ YOLOv2 models and FPGAs, owing to their adaptability and userfriendliness. The Simulink HDL compiler was utilized to design, simulate, and implement our proposed design. In an effort to rectify this, this paper presents a comprehensive programming and design proposal. The implementation of the YOLOv2 algorithm for real-time vehicle detection on the Xilinx® Zynq-7000 System-on-a-chip is proposed in this work. Real-time testing of the synthesised hardware revealed that it can process Full HD video at a rate of 16 frames per second. On the Xilinx Zynq-7000 SOC, the estimated dynamic power consumption is less than 90 mW. When comparing the results of the proposed work to those of other simulations, it is observed that resource utilization is enhanced by around 204 k (75%) LUT, 305 (12%) DSP, and 224 k (41%) flip-flops at 200 MHz. [ABSTRACT FROM AUTHOR]

An adaptive real-time gate scheduling scheme for time perceptive stream or packet flow is proposed to improve the standards of Ultra Low Latency during data transmission. For highly dynamic network conditions, the conventional configuration scheme is not suitable and therefore an adaptive real-time gate scheduling method is proposed for time perceptive streams. This dynamicity reconfiguration is difficult and the scheduling problem is formulated using Field Programmable Gate Array – Boolean Satisfiability Problem (FPGA-BSP) solver. This proposed scheme highly helps in network dynamicity conditions with good bandwidth utilization and high flexibility. End-to-end latency is required to be on sub-milliseconds order deal with the applications such as Industrial Internet of Things, 5G and 6G mobile, tactile internet and so on. Simulation analysis is carried out to prove the efficiency of the proposed model. [ABSTRACT FROM AUTHOR]

The field of reconfigurable computing is gaining a lot of following, and several use cases have been developed for it. At the centre of reconfigurable computing is the field programmable gate array (FPGA) due to its computational speed and versatility. The goal of the work reported here was to show that a single FPGA board paired with a computer monitor can be used as the sole laboratory equipment in a cash-strapped educational institution or by an individual. A Terasic DE1-SoC board was programmed as an oscilloscope, and digital multimeter. In keeping with the low-cost theme of this work, no external signal conditioning circuit was used and the on-board LTC2308 ADC was used for signal acquisition. At frequencies below 15 kHz, the voltage measurements of the developed FPGA lab instrument had a mean error of 58 mV. The voltage measurement errors, however, increased with an increase in frequency and the errors were significant when the signal frequencies exceeded 100 kHz. In terms of the use of the FPGA to replace multiple lab instruments, 13% of the DSPs on the FPGA were used for the implementation and 80% of the Adaptive logic modules. We therefore demonstrate that with $300 dollars, multiple pieces of laboratory equipment can be replaced by a single FPGA board and a monitor. [ABSTRACT FROM AUTHOR]

An Instructional Processor has been developed as a design example in an Advanced Digital Systems course. The architecture is modelled in VHDL and can be simulated using Xilinx design tools. A basic microcontroller is created by adding memory-mapped input/output (I/O). The hardware system can be synthesized and implemented on a field programmable gate array (FPGA). The goal of this project was to add serial communication capabilities via software and a hardware UART (universal asynchronous receiver transmitter). The design allows direct access to the UART data registers (receive and transmit), status register (flags), and control register (baud rate). Test programs, written in assembly language, were used to verify the communication protocol and timing via VHDL simulation. The FPGA microcontroller was able to communicate with serial devices at various baud rates. The UART gives students an in-depth look at both the internal details and external interfacing of a real-life system. [ABSTRACT FROM AUTHOR]

The artificial intelligence inference model is currently the best mathematical model based on artificial neural networks. The intelligent reasoning mode based on artificial intelligence has a large construction scale. In a completed inference, many multiplication and addition operations need to be completed. To establish an effective artificial intelligence inference model, its computational complexity is dozens or even more times higher than traditional artificial intelligence algorithms. This article focused on the research on the isomerization acceleration of FPGA (Field Programmable Gate Array). This article was looking for a method that reduces both system changes and migration, while maximizing the flexibility of FPGA programmability. In order to build on this foundation, a fast interface for fast computation using FPGA was designed. The characteristic of this project was that it could combine the FPGA acceleration platform with ordinary computers or servers, and could effectively utilize traditional computer software and toolchains. This article compared the computational time consumption between the inference model and the CPU. In the scale calculation logic scenario of the inference model designed in this article, it could achieve the same computing power as the CPU when processing 70000 multiplication calculations. The experimental results indicated that the increase in CPU computing power was greater than that of the inference model. This indicated that the larger the amount of computational data, the more significant the acceleration effect of the inference model in this article would be. [ABSTRACT FROM AUTHOR]

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks. The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs' capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost. [ABSTRACT FROM AUTHOR]

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks. The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs' capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost. [ABSTRACT FROM AUTHOR]

Due to recent developments in high-energy laser systems, the laser is becoming one of the most potential choices in battlefield applications. Laser of a laser range finder used to find target distance may be of nanosecond pulse width and a single pulse may be sufficient to gather the instantaneous range information. A laser target designator is a similar laser with higher energy and with programmable pulse repetition frequencies5,7. Detection of such a specific battlefield laser radiation along with recognizing friend or foe is required for countermeasures. Designing a laser detection system that is capable of detecting such low-power level laser pulses of nanosecond pulse width at a long distance is a critical design and a challenging task. Again detecting a wide wavelength band that can start from 500 nm to around 1700 nm range using a single detector or device is also a challenging task. In this work, a sensor system is being designed and a prototype is developed to cover such a long band detection using a single detector for high-energy lasers. Also, in addition to detecting hostile code, the direction of an incoming laser beam is tried to incorporate into this sensor. The sensor can be utilized to detect unknown or non-friendly laser illumination from within a specific angular cone and distance. [ABSTRACT FROM AUTHOR]

Model Predictive Control (MPC) has attracted much attention and is widely used in power electronics. However, implementing the MPC algorithm is still a difficult task due to the fast dynamics of power converters and strict time constraints. In this paper, a computationally efficient MPC algorithm for grid-tied power converters based on the fast gradient projection method and invariant set theory is proposed. The algorithm is implemented and tested through hardware-in-the-loop simulations using Texas Instruments digital signal processors and Xilinx Field Programmable Gate Arrays platforms. [ABSTRACT FROM AUTHOR]

Since the end of the 1990s, cryptosystems implemented on smart cards have had to deal with two main categories of attacks: side-channel attacks and fault injection attacks. Countermeasures have been developed and validated against these two types of attacks, taking into account a well-defined attacker model. This work focuses on small vulnerabilities and countermeasures related to the Elliptic Curve Digital Signature Algorithm (ECDSA) algorithm. The work done in this paper focuses on protecting the ECDSA algorithm against fault-injection attacks. More precisely, we are interested in the countermeasures of scalar multiplication in the body of the elliptic curves to protect against attacks concerning only a few bits of secret may be sufficient to recover the private key. ECDSA can be implemented in different ways, in software or via dedicated hardware or a mix of both. Many different architectures are therefore possible to implement an ECDSA-based system. For this reason, this work focuses mainly on the hardware implementation of the digital signature ECDSA. In addition, the proposed ECDSA architecture with and without fault detection for the scalar multiplication have been implemented on Xilinx field programmable gate arrays (FPGA) platform (Virtex-5). Our implementation results have been compared and discussed. Our area, frequency, area overhead and frequency degradation have been compared and it is shown that the proposed architecture of ECDSA with fault detection for the scalar multiplication allows a trade-off between the hardware overhead and the security of the ECDSA. [ABSTRACT FROM AUTHOR]

Document Image Binarization is one of the image enhancement techniques and has potential applications in the field of Document Image Analysis and Recognition (DIAR). During the DIAR process, different types of noise such as uneven illumination, clutter, margin, skew, bleed-through and show-through are removed. However, the removal of show-through noise is a challenging task because it affects mostly the document image quality and readability. In this work, we have designed and developed a model-based point processing operation, which is implemented in the Altera Cyclone® V DE1-SoC for removing the show-through noise and enhancing the degraded document image quality. The Altera Cyclone® V DE1-SoC board was chosen for this study due to its performance, size compatibility, and real-time implementation, which are better than the programmable DSP chips. The Pixel/Point processing operations were implemented using the DSP builder tool, which boost-up better execution of computational operations involved in complex algorithms. To implement the proposed algorithm, we have developed the board library file for Altera Cyclone® V DE1-SoC series 5CSEMA5F31C6 board in DSP builder and tested on various document images. The calculated quality measures of the proposed algorithm tested on various document images in the FPGA board exhibited better results in terms of document image readability, quality, processing speed, and memory size. Further, the performance of the proposed algorithms was studied in different scanned document images dataset as well as with the other traditional techniques. The results of this study witnessed that the proposed model-based point processing methods performs very well than the other methods. [ABSTRACT FROM AUTHOR]

To digitalize the wire EDM process, data-driven models are necessary for evaluating its performance. This presents a challenge due to the high volume of data and the stochastic nature of the process. In this paper, electrical parameters are measured and processed by an FPGA (field programmable gate array) system to recognize and characterize temporally and spatially resolved single discharges as either normal or abnormal. Supervised machine learning methods such as artificial neural networks (ANN) are used and models are trained with different data sets to predict the machined geometrical accuracy and cutting speed based on recorded process data. [ABSTRACT FROM AUTHOR]

This paper implements an artificial neural network (ANN)-based engine model using the Field Programmable Gate Array (FPGA). The developed (ANN)-based engine model will be used to estimate the engine gas emissions to mitigate the harmful effects of these emissions on human health. Getting reliable and robust FPGA-based ANNs implementations depends on the optimal choice of activation function that will provide minimal area occupation on FPGA. This study introduces, implements, and investigates FPGA-based ANN-based engine models using five different activation functions. These implemented engine models were described using MATLAB/Simulink and hardware description language coder and carried out by Spartan -3E-500.CP132 FPGA platform from Xilinx. The performance of the implemented engine models was investigated in terms of area-efficient implementation and the regression values (R) to build a robust ANN-based engine model. [ABSTRACT FROM AUTHOR]

Cryptographic circuits, because they contain confidential information, are subject to fraudulent manipulations, commonly called attacks, by ill-intentioned people. Several attacks have been identified and analyzed. One of the most efficient attacks, called DFA (Differential Fault Analysis) cryptanalysis, exploits the presence of faults, injected voluntarily by the attacker, for example with a laser, in the calculations. Countermeasures are then developed and validated to protect the hardware implementation of cryptographic algorithms such as AES algorithm. The present paper aims to protect the AES algorithm against fault injection attacks. In this paper, an efficient fault detection method for the AES algorithm has been developed. In our proposed design, the AES round architecture is devised into three parts and two pipelines registers are inserted in between. Our simulations show that fault detection capabilities of the proposed method for random fault archives 99.539%. The error detection structure can detect the inserted faults with good coverage using the proposed approach. In order to verify the accuracy of our results, we compare our implementation result with the results presented in the literature. Note that the results obtained are competitive with existing implementations. Our fault detection method has the ability to achieve a compromise of safety level and low implementation cost. [ABSTRACT FROM AUTHOR]

Cryptographic circuits, because they contain confidential information, are subject to fraudulent manipulations, commonly called attacks, by ill-intentioned people. Several attacks have been identified and analyzed. One of the most efficient attacks, called DFA (Differential Fault Analysis) cryptanalysis, exploits the presence of faults, injected voluntarily by the attacker, for example with a laser, in the calculations. Countermeasures are then developed and validated to protect the hardware implementation of cryptographic algorithms such as AES algorithm. The present paper aims to protect the AES algorithm against fault injection attacks. In this paper, an efficient fault detection method for the AES algorithm has been developed. In our proposed design, the AES round architecture is devised into three parts and two pipelines registers are inserted in between. Our simulations show that fault detection capabilities of the proposed method for random fault archives 99.539%. The error detection structure can detect the inserted faults with good coverage using the proposed approach. In order to verify the accuracy of our results, we compare our implementation result with the results presented in the literature. Note that the results obtained are competitive with existing implementations. Our fault detection method has the ability to achieve a compromise of safety level and low implementation cost. [ABSTRACT FROM AUTHOR]

High Voltage High Pulse Power Supply (HVHPPS) is designed with the goal to match fixed load, so that precise pulse output can be achieved. Generally the loads involve magnetron, klystron, and particle accelerators etc. The HVHPPS output pulse shape changes with load impedance variation due to various reasons. Due to changes in impedance, the performance of Pulse Power Supply degrades and reflects the power at the source end which causes component failure and system shut down. To overcome such problems, a scale down High Voltage High Pulse Power is designed and developed to match the dynamic impedance variations upto 25 % of mismatch. In earlier days, all HVHPPS were designed using microcontrollers where the problem of pulse to pulse monitoring and computational speed was compromised. The availability of variable and self-defined, Field Programmable Gate Array (FPGA) controller, which provided flexibility to design the pulse to pulse shaping and various vital parameter monitoring, made it possible. This paper presents the design and implementation of HVHPPS over an FPGA platform to meet the fast response requirement. This paper provides a solution for impedance mismatch problems associated with such types of power supply, and also presents specifications for major components in a high voltage pulse power system for various types of load ranges. An experimental test hardware was designed and developed for HVHPPS to implement dynamic impedance algorithm and validate the results. [ABSTRACT FROM AUTHOR]

In this study, the fuzzy-based reference flux estimator (RFE), reference torque estimator (RTE) and sector rotation strategy called fuzzy logic estimator are proposed to direct torque control of induction motor (DTC-IM) drive for performance improvement. The basic DTC-IM drive with conventional RFE, RTE and sector division causes large torque ripple, variable switching frequency and uneven voltage vector contribution in stator flux. The torque and speed responses of the proposed system are investigated with load variations. The simulation results of the proposed DTC-IM drive are compared with the basic DTC-IM drive. The assessment of the proposed system shows improved performance. A hardware is developed using Xilinx Spartan-6XC6SLX45-Field Programmable Gate Array (FPGA) Kit for experimental verification of the results. Moreover, sinusoidal pulse width modulation and space vector pulse width modulation techniques are applied to reduce the torque ripples. The performance of the drive is investigated for various speed ranges. The comparison of the simulated and experimental results proves that the proposed fuzzy-based DTC-IM drive provides better performance than the basic DTC-IM drive. [ABSTRACT FROM AUTHOR]

Frequency hopping is a main technique for wireless communication, avoiding interference and interception. This paper provides novel hardware design for frequency-hopping pseudorandom bit generator (PRBG).PRBG design by chaotic maps on FPGA.Two proposed methods in this work first combine chaotic maps in a cascade manner called fixed point cascade chaotic maps (FPCCM-FHSS), and second, the conjunction of chaotic maps done in an XORed manner called fixed point an XOR chaotic method (FPXORCM-FHSS).The results were the first eight NIST randomness tests.Frequency indicates that all p-values larger than 0.01 are needed to achieve better randomness,Second and third were die-hard tests, many distribution tests with significant p-values (p <0.01) that meet high standards of statistical randomness, making them suitable for channel security.Last were the FPGA results between the proposed methods for speed and hardware resources).The works implemented on XILINX ZC702 achieved 2 Gbps to meet the speed requirements of the change of the carrier frequency. [ABSTRACT FROM AUTHOR]

Accelerating neural network (NN) controllers is important for improving the performance, efficiency, scalability, and reliability of real-time systems, particularly in resource-constrained embedded systems. This paper introduces a novel weight-dropout method for training neural network controllers in real-time closed-loop systems, aimed at accelerating the embedded implementation for solar inverters. The core idea is to eliminate small-magnitude weights during training, thereby reducing the number of necessary connections while ensuring the network's convergence. To maintain convergence, only non-diagonal elements of the weight matrices were dropped. This dropout technique was integrated into the Levenberg–Marquardt and Forward Accumulation Through Time algorithms, resulting in more efficient training for trajectory tracking. We executed the proposed training algorithm with dropout on the AWS cloud, observing a performance increase of approximately four times compared to local execution. Furthermore, implementing the neural network controller on the Intel Cyclone V Field Programmable Gate Array (FPGA) demonstrates significant improvements in computational and resource efficiency due to the proposed dropout technique leading to sparse weight matrices. This optimization enhances the suitability of the neural network controller for embedded environments. In comparison to Sturtz et al. (2023), which dropped 11 weights, our approach eliminated 18 weights, significantly boosting resource efficiency. This resulted in a 16.40% reduction in Adaptive Logic Modules (ALMs), decreasing the count to 47,426.5. Combinational Look-Up Tables (LUTs) and dedicated logic registers saw reductions of 17.80% and 15.55%, respectively. However, the impact on block memory bits is minimal, showing only a 1% improvement, indicating that memory resources are less affected by weight dropout. In contrast, the usage of Memory 10 Kilobits (MK10s) dropped from 97 to 87, marking a 10% improvement. We also propose an adaptive dropout technique to further improve the previous results. [ABSTRACT FROM AUTHOR]

Non-cryptographic (NC) hash functions are generally designed for speed and efficiency, which enables their use in many network security applications that require efficient lookup and counting, such as Bloom Filters and Count-Min (CM) Sketch structures. The performance of these structures heavily relies on underlying hash functions. Therefore, any advancement in the hash function design significantly impacts the overall performance of these structures. This paper presents a novel family of 32-bit NC hash functions (NCGPH-32) evolved using Genetic Programming (GP) and their corresponding implementation on Field Programmable Gate Arrays (FPGAs). This family of NC hash functions generates smaller hash values concatenated to produce larger hash outputs. Inspired by related work on 96-bit NC hash functions with GP, this work optimizes the performance of 32-bit NC hash functions on FPGA while achieving high scores on specific avalanche metrics (avalanche dependence, avalanche weight, and entropy) when considering concatenated 96-bit outputs. This optimization is of utmost importance to address the escalating demand for Terabit Ethernet networks, specifically in processing real-time network flow IDs (identification and monitoring) at line rate. The throughput, latency, operating frequency, and resource utilization are evaluated on an FPGA and compared against 17 state-of-the-art NC hash functions. The results show that the proposed 96-bit concatenated hash function surpasses prior GP-based and other state-of-the-art NC hash functions by at least 36% in operating frequency, 30% in throughput and reduces latency by 27%. The demonstrated improvements in the hash design not only cater to the present demands of Terabit networks but also meet the expected near-future demands. Additionally, we integrate these hash functions into the Standard Bloom Filter (SBF) architecture and demonstrate comparable false positive rates (FPR) to state-of-the-art NC hash functions, affirming their effectiveness and applicability. We have also conducted several statistical tests on hash outputs of NCGPH-32 to demonstrate the high random nature and uniform distribution. • Proposed a novel 32-bit hash family for 96-bit inputs using Genetic Programming (GP). • Concatenated the three best hash outputs from the 32-bit hash family to produce 96-bit output. • The proposed design surpasses the state-of-the-art Non-Cryptographic (NC) hash functions by at least 36% in operating frequency, and 30% in throughput and reduces latency by 27% on FPGA. • Integrated the hash functions in a Standard Bloom Filter and showed that the False Positive Rate is comparable to state-of-the-art NC hash functions. • The proposed NC hash functions exhibit favourable uniformity characteristics. [ABSTRACT FROM AUTHOR]

Great interest is directed toward real-time applications to determine the exact location of sensor nodes deployed in an area of interest. In this paper, we present a novel approach using a combination of the Kalman filter and regularized bounding box method for localizing unknown nodes in an area using an FPGA-enhanced edge computing UAV whose trajectory is known and is represented as the position of many anchors. The UAV is equipped with a GPS system that allows it to gather location data of sensor nodes as it moves around its environment. We employ a regularized bounding box to predict the positions of the unknown nodes using regularization factors and we use the Kalman filter algorithm to smooth and improve the accuracy of the sensor nodes to be localized. In order to localize the unknown nodes, the UAV receives the number of hops from each node and uses this information as input to the localization algorithm. Furthermore, the use of an FPGA board allows for real-time processing of sensory data, enabling the UAV to make fast and accurate decisions in dynamic environments. The localization algorithm was implemented on the FPGA board "Zynq MiniZed 7007s evaluation board" using Xilinx blocks in Simulink, and the generated code was converted into VHDL using Xilinx System Generator. The algorithm was simulated and synthesized using "Vivado" software. In fact, the proposed system was evaluated by comparing the performances achieved through two different implementations: Hardware and Software implementation. In effect, the performance of FPGA hardware implementation presents a new achievement in localization due to its easy testing and fast implementation. Our results show that this approach can efficiently locate unknown nodes with good latency and high accuracy. In fact, the execution time of the FPGA-integrated algorithm is reduced by about 60 times compared to the software implementation and the power consumption is about 100 mW, which proves the suitability of FPGA for localization in WSNs, offering a promising solution for various mobile WSN applications. [ABSTRACT FROM AUTHOR]

This paper explores new methods to increase the level of safety of data transfer between sensors and electronic control units (ECUs) in automotive communication. A new model of basic sensors to be used in automotive electronics is proposed. This model contains hardware modules that implement the end-to-end communication protection (E2E) mechanism, as defined by the Automotive Open System Architecture (AUTOSAR) standard. By adding this feature inside the sensors, it is possible that, in addition to increasing the safety level, these sensors can be directly connected to the network ECUs via standard communication buses (e.g., Local Interconnect Network (LIN), Controller Area Network (CAN), Flexray, etc.). This paper describes the model, design, and mapping (in a Field Programmable Gate Array device (FPGA)) of the hardware E2E module capable of generating the Cyclic Redundancy Code (CRC) and counter signal for a customized message. This message represents the output of the new sensor E2E module used in a safety communication as requested by the automotive E2E standard. The model is validated also by comparing the data output of the E2E hardware with the data output of the AUTOSAR software E2E library. Finally, future needs and directions are suggested in this area. [ABSTRACT FROM AUTHOR]

The improved k-nearest neighbor (KNN) algorithm based on class contribution and feature weighting (DCT-KNN) is a highly accurate approach. However, it requires complex computational steps which consumes much time for the classification process. A field programmable gate array (FPGA) can be used to solve this drawback. However, using traditional hardware description language (HDL) to implement FPGA-based accelerators requires a high design time. Fortunately, the open computing language (OpenCL) high level parallel programming tool allows rapid and effective design on FPGA-based hardware accelerators. In this study, OpenCL has been used to examine speeding up the DCT-KNN algorithm on the FPGA parallel computing platform through applying numerous parallelization and optimization techniques. The optimized approach of the improved KNN could be used in various engineering problems that require a high speed of classification process. Classification of the COVID-19 disease is the case study used to examine this work. The experimental results show that implementing the DCT-KNN algorithm on the FPGA platform (Intel De5a-net Arria-10 device was used) gives an extremely high performance when compared to the traditional single-core-CPU based implementation. The execution time for our optimized design on the FPGA accelerator is 44 times faster than the conventional design implemented on the regular CPU-based computational platform. [ABSTRACT FROM AUTHOR]

The security of data is a major concern in this digital era. In general text and image data are well protected with the help of existing standards, meanwhile, securing voice communications is a challenging task. In the literature, there are some methods found using oscillators and chaotic signals for protecting direct voice communications, but they have limited functionalities due to synchronization problems between chaotic signals and oscillators. This paper gives an idea of encrypting voice signals over peer to peer communication with the help of a modified and lightweight AES algorithm. This algorithm is similar to the traditional AES algorithm in most of the aspects but does not imply the use of mix column that is used in the traditional AES algorithm. The lightweight algorithm is tested on two different Field Programmable Gate Array (FPGA) and the designs are analyzed with respect to time delay and effective utilization of resources. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Harbin Institute of Technology. Social Sciences Edition / Haerbin Gongye Daxue Xuebao. Shehui Kexue Ban is the property of Harbin Institute of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The biggest problem that electric or hybrid vehicles present today are the amount of time required to recharge their energy, hence the importance of ensuring that the charge is not lost quickly and reducing the recharging time. We propose a more efficient energy production model to maintain the charge of the battery banks in hybrid and electric vehicles so that the autonomy time increases. A direct current to direct current (DC-DC) converter was modeled, in a buck-boost configuration that can keep the voltage constant of 50VDC powering the battery bank, with input voltages ranging between 35 and 70VDC with a fixed charging current of 4A. To automatically determine the values of the discrete components of the power filter, a MATLAB® script was developed. The transfer function of the power filter controller was calculated and simulated in open and closed loops to analyze the converter's stability. The complete circuit was tested for possible variations in voltage and load current using a Pulse-Width Modulation (PWM), with a time base of 2.4 kHz. To demonstrate the ability to perform the same function of the converter in a more stable way, digital control by PWM was implemented on a Nexys 4 development board (FPGA, Field Programmable Gate Arrays). In addition, with the advantage of reducing the variations inherent in using discrete components in an electronic circuit. Herein we disclose 1. a high-level language computer program to estimate the value of the components of the power filter that performs the energy conversion; 2. the transfer functions of the system modules; 3. the simulation of the buck-boost DC-DC converter control system without polarity inversion; and 4. the simulation of the system in digital form implemented on an FPGA. [ABSTRACT FROM AUTHOR]

Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task. The routing of WSN is classified as proactive, reactive, and hybrid. Adhoc on-demand distance vector (AODV) routing is an example of reactive routing based on the demand route formations among different nodes in the network. The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated synthesis environment (ISE) 14.7 software. The performance of the chip is studied based on the field-programmable gate array (FPGA) hardware parameters such as slices, lookup table (LUTs), input/output block (IOB), flipflops, and memory for the different configurations of the network (N = 10, 20 ....100). The delay and frequency are also estimated on the Virtex-5 FPGA. The performance of the WSN with AODV routing is also analyzed based on the packet delivery ratio, throughput, delay, and control overhead. The simulation test cases verified the 8-bit, 64-bit, and 128-bit data communication within the nodes. [ABSTRACT FROM AUTHOR]

The statistical weakness problem occurring as a result of physical randomness is an important shortcoming of TRNGs. Post-processing techniques are generally used in the literature to overcome this shortcoming. In this study, the hardware implementation of Advanced Encryption Standard (AES) substitution box (s-box)-based novel post-processing technique is presented. The low-cost novel method is based on the substitution s-box transformations and can successfully remove the statistical weakness problem of TRNGs. The real-time verification of the proposed post-processing is done by applying ring oscillator (RO) based TRNG architecture in four different scenarios on Field Programmable Gate Array (FPGA) environment. Successful statistical results obtained from bias, correlation, entropy and NIST 800-22 tests confirm the usability of the proposed method for cryptographic purposes. The low area-energy requirement, practicality and compressionless properties of the post-processing provide better tradeoff for TRNG compared to known methods in the literature. For this reason, TRNG's performance is high. Furthermore, the presented study is important in demonstrating that s-boxes with good mathematical encryption properties can also be used for different cryptographic purposes. [Display omitted] • In this study, a novel Advanced Encryption Standard (AES) substitution box (s-box)-based post-processing technique is proposed. • The compressionless feature of the post-processing eliminates the limiting effects such as entropy and output bitrate loss caused by the known methods on True Random Number Generators (TRNGs). • Since the area-energy requirement of the post-processing technique is low, it can be easily used in resource-restricted architecture and applications. [ABSTRACT FROM AUTHOR]

This paper introduces an innovative unified deep learning (DL) model, "reduced deep convolutional stack autoencoder (RDCSAE)-robust kernel-based random vector functional link network (RKRVFLN)" (RDCSAE-RKRVFLN), for addressing practical challenges like phase and gain uncertainty, mutual coupling effects, and element position errors in direction of arrival (DOA) estimation. The RDCSAE utilizes deep convolutional neural network (DCNN) and stack autoencoder (SAE) for robust feature extraction. The RKRVFLN integrates a concise SAE output with kernel-based learning. Thus, the integration of RDCSAE (suitable for unsupervised feature extraction) and RKRVFLN (for supervised learning) in the developed model results in efficient use of limited training data. Performance metrics of this method include among others the accuracy (separation between sources), root mean square error (RMSE), signal-to-noise ratio (SNR), etc. The method performs better than existing data driven methods in terms of computational efficiency, faster learning speed, enhanced model generalization, higher accuracy, and shorter event regression time and empirical methods. In the presence of above mentioned four perturbations, this method successfully resolves multiple sources with a resolution of 0. 3 ° with a RMSE of 0.00376. For real time application, the paper implements RDCSAE-RKRVFLN on a high-speed reconfigurable Xilinx Virtex-5 field-programmable gate array (FPGA) realizing a digital DOA estimator for one source. The hardware estimates the DOA with a maximum error of 0.01953125 which follows closely the simulation results indicating the efficiency and feasibility of the method. • A framework in the presence of array imperfection for the direction of the arrival estimation problem. • Reduced deep convolutional stack autoencoder network architecture produces high-level discriminative representations. • The less computational complex robust kernel RVFLN regression method shows outstanding performance. • An FPGA implementation proves the developed method's robustness for direction finding. [ABSTRACT FROM AUTHOR]

Attractors with multiple wings and many scrolls remain captivating for the number and variety of non-linear bifurcations they display. Then, other features related to these attractors like hyper-chaos, fractal, hidden attractor, strange attractor are also significant. This paper analyzes and implements another important attractors' feature, related to generating their mirror symmetrical projections which also conserve the original properties. The generation of that mirroring process is possible thanks to the perturbation with the duality-symmetrical operator ϵ and the mirror conversion function λ , that have been incorporated into a variable order four dimensional system of chaotic attractors with many scrolls (CAMS). We first solve the model numerically and analyze the committed error then, we study the system's state of disorder, stability and randomness. Numerical simulations are performed and show existence of the model's CAMS in their mirroring structure, where the mirror images share identical properties. Lastly, a programmed circuit implementation is done making used of a digital-to-analog converter (DAC) and a Field Programmable Gate Array (FPGA) board. The obtained digital outputs via the Rigol digital oscilloscope (RDO) correspond to the intended outcomes, those found in the analytical-numerical part of the work. [ABSTRACT FROM AUTHOR]

The existing Programmable Logic Controller (PLC) based on microprocessors (μ p) or micro-controllers (μ c) are commonly used in the industry for various instrumentation and control applications. PLC exhibits limitations such as less flexibility, poor scanning time, slower speed, and degraded response for high-speed industrial applications due to its fixed hardware and serial execution mechanism. A new Field Programmable Gate Array (FPGA) based PLC multi-channel High Speed Counter (HSC) module has been proposed, enhancing performance and flexibility compared to the existing PLC-HSC module. The proposed FPGA-PLC-HSC module has a 2-phase 2-Input counter with resolutions of 1X, 2X, and 4X which improve performance in terms of accuracy for position speed, and direction measurement applications. The FPGA-PLC-HSC module is implemented with the feedback node method and the shift register method inside LabVIEW FPGA along with device utilization. The simulation results show that the FPGA-PLC-HSC module has faster scanning time, good linearity, better resolution, maximum supporting input frequency, and counting frequency. For experimental purposes, an optical encoder M110960 (E8P-512-118-S-D-M-B) with a signal conditioning circuit is connected to the NI-myRIO-1900 FPGA platform. The experimental results point out that the proposed FPGA-PLC-HSC module offers faster scanning time, better accuracy and linearity in 1X, 2X, and 4X resolution. [Display omitted] • FPGA-PLC-HSC module is proposed with high resolution, linearity, and flexibility. • It is used to enhance performance for speed, position, and direction measurement applications. • The reported accuracy is ± 0.2675%, ± 0.1689%, and ± 0.12% in 1X, 2X and 4X resolution, respectively. • Proposed module offers less scantime, fast speed, and cost-effectiveness solution. [ABSTRACT FROM AUTHOR]

In this paper, a Four Dimensional Space Vector Modulation (4D-SVM) is implemented for five phase Voltage Source Inverter (VSI) to improve the performance of the inverter. The 4D-SVM control technique generates switching pulses for five phase VSI system. The reference vector for 4D-SVM is identified by tracking subcubes and prisms located in the complex 4D-cubic region. The 4D-SVM for five phase inverter includes 32 switching state vectors; all the switching states are non-redundant switching states, which are located in 32 vertices of the 4D-cube. The proposed five phase inverter with 4D-SVM reduces CMV and Total Harmonic Distortion (THD) and minimized neutral current value. The minimization of CMV leads to avoid the damage of the winding and increases the life time of the motor. So for in two level inverter, the CMV is reduced up to V dc /3 times of input voltage; In this proposed system, made an attempt to reduce the CMV level below this reported value. The simulation and hardware results are verified using matlab simulink and Field Programmable Gate Array (FPGA) processor. [ABSTRACT FROM AUTHOR]

The Discrete Zolotarev Transform (DZT) brings an improvement in the field of spectral analysis of nonstationary signals. However, the transformation algorithm called Approximated Discrete Zolotarev Transform (ADZT) suffers from high computational complexity. The Short Time ADZT (STADZT) requires high segment length, 512 samples, and more, while high segment overlap to prevent information loss, 75% at least. The STADZT requirements along with the ADZT algorithm computational complexity result in a rather high computational load. The algorithm computational complexity, behavior, and quantization error impacts are analyzed. We present a solution which deals with high computational load employing co-design methods targeting Field Programmable Gate Array (FPGA). The system is able to compute one-shot DZT spectrum 2 048 samples long in ≈ 22 ms. Real-time STADZT spectrum of a mono audio signal of 16 kHz sampling frequency can be computed with overlap of 91%. [ABSTRACT FROM AUTHOR]

This paper describes a model predictive control method for Nine-Switch Inverter (NSI)-based AC drive systems. Two separate three-phase AC loads (dual-output mode operation) or a single six-phase load (six-phase mode operation) can be connected to output terminals of an NSI. Three different Finite Control Set Model Predictive Control (FCS-MPC) strategies are presented and described. Firstly, dual-output mode FCS-MPC provides flexible control of detached load stages without any undesirable interaction. When disseminated loads are needed to be controlled, the output terminals of NSI are individually connected to separate load stages. Secondly, six-phase mode FCS-MPC provides robust control of six-phase load current. Thirdly, the predictive control scheme for controlling multiple induction machines is presented. Experimental and simulation tests have demonstrated that the proposed method exhibits a secured converter operation. The proposed predictive control strategies of Nine-Switch Inverter are accomplished using a Field Programmable Gate Arrays (FPGA). • Dual-output mode MPC provides independent control of two seprate loads. • Six-phase mode MPC provides robust control of six-phase load fed by NSI. • Dual-predictive torque control method is experimentaly validated. • Detailed design steps of multi-step MPC of NSI are presented. [ABSTRACT FROM AUTHOR]

Beam wandering and the wavefront distortion are the significant sources for the power loss in Wireless Optical Communication (WOC). In this paper Full Factorial Design (FFD) and Back Propagation Neural Network (BPNN) controller based autonomous beam monitoring, positioning and recovery system for fine steering of the laser beam at the focal point of the FSOC receiver is proposed. The proposed controllers process the intensity information of the received optical beam as inputs and produce the control signals as outputs. These control signals bring the beam at the focal point of the receiver and avoid the power loss of the optical link. The work describes performance analysis of Field Programmable Gate Array (FPGA) based novel digital architecture of FFD and BPNN controller. Real time experimental verification of the stability and suitability of the developed adaptive controllers are tested for percentage of prediction error, Bit Error Rate (BER) and beam wander reduction ability and the same is demonstrated with suitable results. The experimental result shows that the BPNN controller gives high accurate approximation towards the control for the control signals Cx and Cy with the minimum and maximum values of 99.29% and 99.86% respectively. With the chosen parameters, the neuro-controller exhibits fast response for the error changes. The proposed BPNN controller provides prediction error very close to -0.5 to +1.0%, the values lie in the range of -0.06781% and 0.9862% which shows that the BPNN controller is efficient for the real time tracking and control for FSOC, LIDAR imaging, micro/nano positioning, atomic force microscopes, scanning tunneling microscopes, etc. [ABSTRACT FROM AUTHOR]

To solve the problem of commercial device with weak anti-SEU ability and traditional radiation hardened device with slow processing speed, this article proposes a novel system-level collaborative triple module redundancy (TMR) design to mitigate single event upset (SEU) on the advanced heterogeneous processor. Based on Xilinx Zynq Ultrascale+ MPSoC, we combine TMR with rolling back, watchdog and scrubbing technique between heterogeneous cores which are Arm Cortex-A53 and Field Programmable Gate Array (FPGA). This combination brings us a promising result of fault identification and correction according to the simulation of the single channel data fault and the double channel data fault. It costs 27%-44% more time to process error and the system has relatively low resource utilization rate and power consumption. Moreover, it can also apply to general heterogeneous quad-core System on Chip (SoC) with FPGA processor's anti-SEU design and provides some ideas for further study of system level radiation-resistant chips' design. [ABSTRACT FROM AUTHOR]

DATuner is an autotuning program, but its running time is very long and uneven. In our paper, a novel methodology for autotuning and exploring parameter space is proposed. Combined with Structural Equation Model and statistical techniques, the prior pruning was proposed. Firstly, using benchmarks in DATuner, VTR (Verilog to Routing) was run to generate training data set; Secondly, with training data set as input, modeling software —— AMOS was run to construct structural equation model, and then model was validated and evaluated. If the fitness of the model does not reach requirement, then the connections between variables are modified to get final model whose fitness is sufficient. Finally, the parameters' correlation was analyzed which resulted in routing failure. Applying the prior pruning to DATuner, its autotuning time is reduced and running efficiency has been improved. Compared with unmodified DATuner, DATuner with prior pruning decreases by an average of 44% on the autotuning time. The proposed method greatly improves autotuning efficiency. In addition, DATuner's framework was optimized. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Harbin Institute of Technology. Social Sciences Edition / Haerbin Gongye Daxue Xuebao. Shehui Kexue Ban is the property of Harbin Institute of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Augmented Reality (AR) is a sensational paradigm where real world experiences are enhanced by virtual environment based on computer vision recognition algorithms for physical objects. The real-time image and video processing is challenging because of its computation and complex functions. Field Programmable Gate Arrays (FPGAs) with their reconfigurable architectures provide flexibility, better performance and high levels of parallelism. This paper proposes the implementation of AR using reconfigurable hardware such as Xilinx Zynq SoC (System on a Chip) based on SURF (Speeded-Up Robust Feature) algorithm. The integration of AR and reconfigurable hardware for realtime image processing applications such as detection and feature extraction of images is presented. The implementation results achieve better resource utilization of approximately about 4% of flip-flops, 12% of Look-up Tables (LUTs), 3% of DSP slices and 38% of Block RAMs (BRAMs) for object recognition images with 640x480 resolutions. [ABSTRACT FROM AUTHOR]

The development of systems that can predict epileptic seizures in real-time offers great hope for epilepsy patients. These systems aim to prevent accidents that patients may experience caused by the loss of consciousness during seizures. Therefore, patients must use real-time epileptic seizure prediction systems that do not interfere with their daily activities. In this study, using the unipolar EEG data from a surface electrode, a patient-specific estimation system is implemented in real-time on a system on chip (SoC) that contains an embedded processor and programmable logic blocks. The European epilepsy database EPILEPSIAE is used in the scope of this work. In the proposed system, pre-processing is applied to the EEG data. Then, the features of the data in the frequency domain are extracted. The classifier model is trained with the RusBoosted Tree cluster classifier, which is a machine learning algorithm. Testing is carried out using the proposed classification model. Threshold values are determined, and then false alarms and erroneous classifications are prevented by post-processing. At the end of the tests, prediction success, sensitivity (SEN), Specificity (SPE), False Prediction Rate (FPR), and prediction times are obtained as 77.30%, 95.94%, 0.041 h−1, and 33.23 min, respectively. The proposed system outperforms other studies in the literature in the number of electrodes, real-time operation, hardware/software architecture, and FPR performance. A wearable seizure prediction system seems to be commercialized according to the results achieved in this study. [ABSTRACT FROM AUTHOR]

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator. [ABSTRACT FROM AUTHOR]

This paper introduces an intensive discussion for the dynamical model of the love triangle in both integer and fractional-order domains. Three different types of nonlinearities soft, hard, and mixed between soft and hard, are used in this study. MATLAB numerical simulations for the different three categories are presented. Also, a discussion for how the kind of personalities affects the behavior of chaotic attractors is introduced. This paper suggests some explanations for the complex love relationships depending on the impact of memory (IoM) principle. Lyapunov exponents, Kaplan-Yorke dimension, and bifurcation diagrams for three different integer-order cases show a significant dependency on system parameters. Hardware digital realization of the system is done using the Xilinx Artix-7 XC7A100T FPGA kit. Version 14.7 from the Xilinx ISE platform is used in both Verilog simulation and hardware implementation stages. The digital approach of such a system opens the door to predict the love relation after sensing the human personality. Also, this study will help in justifying more human emotions like happiness, panic, and fear accurately. Perhaps shortly, this study may combine with artificial intelligence to demonstrate Human-Computer interaction products. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Harbin Institute of Technology. Social Sciences Edition / Haerbin Gongye Daxue Xuebao. Shehui Kexue Ban is the property of Harbin Institute of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents a lossy capacitance measuring circuit which is based on analog lock-in detection technique. Lossy capacitance can be modelled as a pure capacitor connected in parallel with a resistor. The measurement circuit mechanism consists of an excitation signal to drive the lossy capacitance, a transimpedance amplifier to produce a voltage, and a lock-in detection circuit to extract lossy values of capacitance. The lock-in detector multiplies its input with a square wave using switches and filters out high frequencies to give a DC output that is actually in proportional to the measured values. A field programmable gate array is employed to generate direct digital synthesis based sinusoidal excitation signal to generate reference signals required for demodulation and to measure the output of lock-in detection. The phase shift between the excitation signal and reference signals is controlled accurately in digital domain. Thus, due to the phase mismatch, errors are properly reduced. Also, analog phase shifter and analog switch-driving circuits are no longer required. Three different lossy capacitors realized using discrete components are simulated and tested. The maximum relative error is 1.62% for the resistance measurement and 6.38% for the capacitance measurement. [ABSTRACT FROM AUTHOR]