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We propose an analytical approach for calculating the time-to-breakdown of metal-oxide-semiconductor (MOS) systems under different stress conditions. Our method relies solely on fresh ${I}_{\text {g}} {V}_{\text {g}}$ measurements, making it easy to implement. Building on the percolation model and incorporating experimental trends from the literature, we accurately determine the voltage, gate oxide thickness, and temperature dependencies of time-to-breakdown. These calculated values are compared to experimental data under various operating conditions, allowing for a comprehensive assessment. Consequently, we introduce a time-to-breakdown map in the {Temperature-Voltage} space for immediate identification of the maximum stress condition for any target lifetime.

Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( ${T}$ ), referred to as “excess 1/f noise,” observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures.

The passivation of the III-V/high-k interface is of key importance in order to bring these materials into the 7 nm technology node. A high amount of interface states (Dit>1E13 /cm2eV) will trap the electrons and therefore the mobility will drop and the SS (Subthreshold Slope) will degrade. Additional defects present in the oxide near the III-V interface will generate device instabilities: the targeted amount of oxide traps should be below <1.5E10 /cm2 at an operating field of 3.5E6 V/cm in order to meet the 10 years reliability target. In this paper, it will be shown that careful engineering of the ALD process can yield a high quality interface at low CET values (<1.5 nm). However, the oxide trap behavior seems to change only slightly with the ALD process and further improvement of the ALD process is required when introducing the III-V materials into the 7 nm technology node.

The passivation of the III-V/high-k interface is of key importance in order to bring these materials into the 7 nm technology node. A high amount of interface states (Dit>1E13 /cm2eV) will trap the electrons and therefore the mobility will drop and the SS (Subthreshold Slope) will degrade. Additional defects present in the oxide near the III-V interface will generate device instabilities: the targeted amount of oxide traps should be below <1.5E10 /cm2at an operating field of 3.5E6 V/cm in order to meet the 10 years reliability target. In this paper, it will be shown that careful engineering of the ALD process can yield a high quality interface at low CET values (<1.5 nm). However, the oxide trap behavior seems to change only slightly with the ALD process and further improvement of the ALD process is required when introducing the III-V materials into the 7 nm technology node.

We report extensive experimental results on the Negative Bias Temperature Instability (NBTI) of SiGe channel pMOSFETs as a function of the main gate stack parameters. These results clearly show that this high-mobility channel technology offers a significantly improved NBTI robustness compared to Si-channel devices, which can virtually eliminate this critical reliability issue for sub-1 nm EOT devices. The intrinsically superior NBTI robustness is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. Thanks to this effect, both a significantly reduced time-dependent variability in nanoscaled SiGe devices and a reduced low-frequency noise are also observed. Other reliability mechanisms, such as Channel Hot Carriers and Time-Dependent Dielectric Breakdown are shown not to be showstoppers. All these aspects underscore the SiGe channel technology as a very promising alternative to Si pMOSFETs for future CMOS technology nodes.

Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology. The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects. Low and high field transport has been studied by in-depth electrical characterization, showing a high hole-mobility that is enhanced by up to 70% in the strained devices. The important role of pocket implants in degrading the drive current is highlighted. Using a judicious implantation scheme, we demonstrate a significant gain in on-current (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of the gate metal and dielectric, together with the corresponding uniaxial stress engineering, is identified as a promising path for further performance enhancement.

Si1-xGex-channel pFETs can combine enhanced intrinsic performance with a threshold voltage shift, therefore this technology possibly facilitates the use of high-k/metal gate stacks in high-performance applications. This review presents imec's work on a new device concept using Si1-xGex-channels, the implant-free quantum well transistor, that can additionally provide improved short-channel scalability, as well as further performance enhancement when compared to conventional silicon and Si1-xGex-channel pFETs. Furthermore, circuit simulations of Si1-xGex-channel pFETs indicate that this technology shows even more enhanced potential at reduced supply voltages, and also in circuits that allow operation at lower electric fields such as stacked transistors. Finally it is demonstrated that the layout sensitivity of Si1-xGex-channel pFETs is an important concern, especially for variations of the device width. The effectiveness of another stress technique, Si1-xGexSource/Drain, is shown to be decreased when used in combination with Si1-xGex-channel pFETs.