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The paper presents a non-classical architecture called the bottom gate MOSFET with source/drain tie (S/D-tied BG) to improve device reliability. S/D-tied BG MOSFET not only effectively reduce the effects of self-heating but also slightly suppress the short-channel effects.

What is silicon-on-insulator (SOI)? Why SOI? Because of the excellent short-channel effects (SCEs) immunity, SOI group is generally considered to be a very strong candidate in the end of the CMOS (complementary metal-oxide semiconductor) scaling, as compared to bulk silicon. This paper aims to propose a novel device architecture namely self-aligned (SA) Pi-shaped source/drain ultra-thin SOI MOS field-effect transistor (Pi-S/D UTSOI MOSFET). Although this approach is based on simulation, numerical simulations, it demonstrates the trends of electrical characteristics in the proposed structure. This work also illustrates the process simulation and the tradeoff between the self-heating and the short-channel behaviors which are two important attributes of the future scaled-down UTSOI devices.

In this paper, we propose a new Voltage- programming pixel circuit using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) for an active matrix organic light-emitting diode (AMOLED). The proposed a-Si:H TFT pixel circuit, which consists of four p-type switching TFTs, one n-type driving TFT, two additional control signals and one storage capacitor, successfully compensated the OLED current fluctuation caused by threshold voltage shift of a-Si:H TFT and the drop on the supply voltage, the propose pixel circuit has been verified by the simulation work using HSPICE software, the simulation result show that this pixel circuit has high immunity to the variation of a-Si:H TFT characteristics.

This paper examines the effect of block oxide height (HBO) on a self-aligned (SA) source/drain-tied n-shaped block oxide field-effect transistor (S/D-tied nBOFET). According to the simulation results of a two-dimensional (2-D) numerical simulator DESSIS, the height of the block oxide is one of the important parameters for the suppression of short-channel effects (SCEs). Hence, the forming of HBO becomes a key process for designing the proposed structure. We also found out that the higher HBO results in an improvement not only in drain-induced barrier lowering (DIBL) but also in subthreshold swing (SS) chiefly owing to the improved SCEs. In addition, the self-heating effects (SHEs) in silicon-on-insulator (SOI) are reduced because the S/D-tied scheme enhances the thermal conduction of heat accumulated.

In this paper, we present a new vertical MOS device having smart source/body contact (SSBVMOS). This vertical sidewall MOSFET possesses vertical channel, sidewall gate, and body passway which allow the conduction of both the generated carriers and heat. Thus, the fabricated device can achieve low self-heating effect and good suppression of the floating body effect without occupying excessive area.