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Your search keyword '"Perrine Batude"' showing total 3 results
Start Over Author "Perrine Batude" Journal 2017 ieee soi-3d-subthreshold microelectronics technology unified conference (s3s)
3 results on '"Perrine Batude"'

1. Self-heating assessment and cold current extraction in FDSOI MOSFETs

Author

C. Fenouillet-Beranger, Laurent Brunet, Perrine Batude, K. Triantopoulos, G. Reimbold, Gerard Ghibaudo, Mikael Casse, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Nano 2017, and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, Materials science, business.industry, Thermal resistance, Transistor, 01 natural sciences, PMOS logic, Ion, law.invention, law, 0103 physical sciences, Thermal, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Current (fluid), Thin film, business, NMOS logic
Abstract

session: Modeling and Characterization; International audience; We present an experimental study of thermal effects in thin film FDSOI MOSFETs, with a focus on the impact of self-heating effect (SHE) on drain current. We have performed thermal resistance extraction using the gate thermometry method, and calculated the resulting cold drain current (Id0), i.e. without SHE. We demonstrate that SHE is more pronounced in shorter and narrower devices without essential differences between nMOS and pMOS transistors. Our experiments show that although the temperature increases significantly in the channel due to SHE, its effect on the ION performances could be limited at operating voltage.

Published
2017

2. Towards 500°C SPER activated devices for 3D sequential integration

Author

Maud Vinet, Vincent Delaye, Zineb Saghi, Perrine Batude, Benoit Sklenard, J.-P. Colinge, L. Pasini, V. Mazzocchi, Claire Fenouillet-Beranger, R. Berthelon, Laurent Brunet, J. Micout, Joris Lacord, Frédéric Mazen, B. Mathieu, Sylvain Joblot, Quentin Rafhay, Gerard Ghibaudo, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), and ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010)

Subjects
Materials science, Dopant, business.industry, Optoelectronics, Recrystallization (metallurgy), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Dopant Activation, business, Epitaxy
Abstract

session: Monolithic 3D 3; International audience; This work investigates the possibility to reduce the Solid Phase Epitaxy Regrowth (SPER) temperature for dopant activation needed in 3D sequential integration. The electrical results obtained on 28nm FDSOI devices show that 500°C SPER can yield similar performance to that of 600°C SPER and 1050°C spike anneal. This paper highlights the advantages of using a -oriented channel and tilted implantation to successfully reduce the SPER thermal budget. It also confirms that the channel can be used as a seed for the recrystallization. The analysis takes into account the SPER rate dependence on temperature, crystalline orientation, dopant type and dopant concentration.

Published
2017

3. Reliability analysis on low temperature gate stack process steps for 3D sequential integration

Author

C-M. V. Lu, F. Martin, Gerard Ghibaudo, R. Gassilloud, Perrine Batude, G. Reimbold, O. Faynot, C. Fenouillet-Beranger, X. Garros, A. Tsiara, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), nano 2017, and ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010)

Subjects
010302 applied physics, reliability, Negative-bias temperature instability, Materials science, Annealing (metallurgy), business.industry, gate stack, Nanowire, Gate stack, Equivalent oxide thickness, low temperature, Dopant Activation, 01 natural sciences, nanowires, 3D sequential integration, 0103 physical sciences, Optoelectronics, process, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010306 general physics, Forming gas, business, Scaling
Abstract

session: Monolithic 3D 3; International audience; In this study we investigate the effect of some of the steps during a low temperature gate stack process flow, necessary for 3D sequential integration. These are: the nitridation of the high-k layer, the post nitridation annealing temperature and finally, the back end forming gas. Using Time Dependent Defect Spectroscopy, we could evaluate the impact of pre-existing traps on the quality of the gate stack (t 0 reliability) which shows no major differences between the splits, since they all have a low temperature dopant activation process. However, by applying Negative Bias Temperature Instability measurements, we observe that with the split of N 2 /H 2 nitridation, we have the best compromise of a small Equivalent Oxide Thickness and a low degradation. At the same time we see no difference at the stress impact between the two Post Nitridation Anneal temperatures. In that way we are able to move to lower temperatures. Finally, using the Deuterium as a back end forming gas we can have a set of guidelines, for some of the major process steps, to achieve high performance and low degradation, necessary for future scaling.

Published
2017

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